Anomalous DIBL Effect in Fully Depleted SOI MOSFETs Using Nanoscale Gate-Recessed Channel Process

Nanoscale Gate-Recessed Channel (GRC) Fully Depleted- (FD-) SOI MOSFET device with a silicon channel thickness (tSi) as low as 2.2 nm was first tested at room temperature for functionality check and then tested at low temperature (77 K) for I-V characterizations. In spite of its FD-SOI nanoscale thi...

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Main Authors: Avi Karsenty, Avraham Chelly
Format: Article
Language:English
Published: Wiley 2015-01-01
Series:Active and Passive Electronic Components
Online Access:http://dx.doi.org/10.1155/2015/609828
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author Avi Karsenty
Avraham Chelly
author_facet Avi Karsenty
Avraham Chelly
author_sort Avi Karsenty
collection DOAJ
description Nanoscale Gate-Recessed Channel (GRC) Fully Depleted- (FD-) SOI MOSFET device with a silicon channel thickness (tSi) as low as 2.2 nm was first tested at room temperature for functionality check and then tested at low temperature (77 K) for I-V characterizations. In spite of its FD-SOI nanoscale thickness and long channel feature, the device has surprisingly exhibited a Drain-Induced Barrier Lowering (DIBL) effect at RT. However, this effect was suppressed at 77 K. If the apparition of such anomalous effect can be explained by a parasitic short channel transistor located at the edges of the channel, its suppression is explained by the decrease of the potential barrier between the drain and the channel when lowering the temperature.
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issn 0882-7516
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publishDate 2015-01-01
publisher Wiley
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series Active and Passive Electronic Components
spelling doaj-art-4a268805fd864673a52ccce79768fc0d2025-08-20T03:20:12ZengWileyActive and Passive Electronic Components0882-75161563-50312015-01-01201510.1155/2015/609828609828Anomalous DIBL Effect in Fully Depleted SOI MOSFETs Using Nanoscale Gate-Recessed Channel ProcessAvi Karsenty0Avraham Chelly1Applied Physics/Electro-Optics Department, Faculty of Engineering, Lev Academic Center, 21 Havaad Haleumi Street, 9116001 Jerusalem, IsraelAdvanced Semiconductor Devices Lab, Faculty of Engineering, Bar-Ilan University, 52900 Ramat Gan, IsraelNanoscale Gate-Recessed Channel (GRC) Fully Depleted- (FD-) SOI MOSFET device with a silicon channel thickness (tSi) as low as 2.2 nm was first tested at room temperature for functionality check and then tested at low temperature (77 K) for I-V characterizations. In spite of its FD-SOI nanoscale thickness and long channel feature, the device has surprisingly exhibited a Drain-Induced Barrier Lowering (DIBL) effect at RT. However, this effect was suppressed at 77 K. If the apparition of such anomalous effect can be explained by a parasitic short channel transistor located at the edges of the channel, its suppression is explained by the decrease of the potential barrier between the drain and the channel when lowering the temperature.http://dx.doi.org/10.1155/2015/609828
spellingShingle Avi Karsenty
Avraham Chelly
Anomalous DIBL Effect in Fully Depleted SOI MOSFETs Using Nanoscale Gate-Recessed Channel Process
Active and Passive Electronic Components
title Anomalous DIBL Effect in Fully Depleted SOI MOSFETs Using Nanoscale Gate-Recessed Channel Process
title_full Anomalous DIBL Effect in Fully Depleted SOI MOSFETs Using Nanoscale Gate-Recessed Channel Process
title_fullStr Anomalous DIBL Effect in Fully Depleted SOI MOSFETs Using Nanoscale Gate-Recessed Channel Process
title_full_unstemmed Anomalous DIBL Effect in Fully Depleted SOI MOSFETs Using Nanoscale Gate-Recessed Channel Process
title_short Anomalous DIBL Effect in Fully Depleted SOI MOSFETs Using Nanoscale Gate-Recessed Channel Process
title_sort anomalous dibl effect in fully depleted soi mosfets using nanoscale gate recessed channel process
url http://dx.doi.org/10.1155/2015/609828
work_keys_str_mv AT avikarsenty anomalousdibleffectinfullydepletedsoimosfetsusingnanoscalegaterecessedchannelprocess
AT avrahamchelly anomalousdibleffectinfullydepletedsoimosfetsusingnanoscalegaterecessedchannelprocess