A–102-dBm Sensitivity Multichannel Heterodyne Wake-Up Receiver With Integrated ADPLL
This article presents a binary frequency-shift keying (BFSK) heterodyne wake-up receiver (WuRx) with -102-dBm sensitivity at 2.4 GHz. An integrated low-power all-digital phase-locked loop (ADPLL) allows sharp filtering at the intermediate frequency (IF) to improve sensitivity and interference robust...
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| Format: | Article |
| Language: | English |
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IEEE
2024-01-01
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| Series: | IEEE Open Journal of the Solid-State Circuits Society |
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| Online Access: | https://ieeexplore.ieee.org/document/10496457/ |
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| author | Linsheng Zhang Divya Duvvuri Suprio Bhattacharya Anjana Dissanayake Xinjian Liu Henry L. Bishop Yaobin Zhang Travis N. Blalock Benton H. Calhoun Steven M. Bowers |
| author_facet | Linsheng Zhang Divya Duvvuri Suprio Bhattacharya Anjana Dissanayake Xinjian Liu Henry L. Bishop Yaobin Zhang Travis N. Blalock Benton H. Calhoun Steven M. Bowers |
| author_sort | Linsheng Zhang |
| collection | DOAJ |
| description | This article presents a binary frequency-shift keying (BFSK) heterodyne wake-up receiver (WuRx) with -102-dBm sensitivity at 2.4 GHz. An integrated low-power all-digital phase-locked loop (ADPLL) allows sharp filtering at the intermediate frequency (IF) to improve sensitivity and interference robustness. The WuRx achieves an average current consumption of 2.2–<inline-formula> <tex-math notation="LaTeX">$171~\mu $ </tex-math></inline-formula>A range at 16 s to 0.1-s latency with the packet-level-duty-cycling scheme. In addition, it supports up to 60 channels from 2.300 to 2.536 GHz. A signal-to-interference ratio (SIR) of -27/-30/-46 dB is achieved at 3/5/25-MHz offset from the carrier. |
| format | Article |
| id | doaj-art-47508d454c1b41758e3462233f122718 |
| institution | Kabale University |
| issn | 2644-1349 |
| language | English |
| publishDate | 2024-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Open Journal of the Solid-State Circuits Society |
| spelling | doaj-art-47508d454c1b41758e3462233f1227182025-01-25T00:03:04ZengIEEEIEEE Open Journal of the Solid-State Circuits Society2644-13492024-01-014435610.1109/OJSSCS.2024.338738810496457A–102-dBm Sensitivity Multichannel Heterodyne Wake-Up Receiver With Integrated ADPLLLinsheng Zhang0https://orcid.org/0000-0002-5985-9819Divya Duvvuri1https://orcid.org/0000-0003-1243-1484Suprio Bhattacharya2https://orcid.org/0009-0003-5501-3079Anjana Dissanayake3https://orcid.org/0000-0003-3466-5994Xinjian Liu4https://orcid.org/0000-0002-3322-5121Henry L. Bishop5https://orcid.org/0000-0001-7155-6434Yaobin Zhang6Travis N. Blalock7https://orcid.org/0009-0000-6084-0843Benton H. Calhoun8https://orcid.org/0000-0002-3770-5050Steven M. Bowers9https://orcid.org/0000-0002-4243-8663NXP USA, Inc., San Jose, CA, USASilicon Labs, Austin, TX, USADepartment of Electrical and Computer Engineering, University of Virginia, Charlottesville, VA, USACSEM-SA, Neuchâtel, SwitzerlandDepartment of Electrical and Computer Engineering, University of Virginia, Charlottesville, VA, USAAmazon.com, Inc., Redmond, WA, USADepartment of Electrical and Computer Engineering, University of Virginia, Charlottesville, VA, USADepartment of Electrical and Computer Engineering, University of Virginia, Charlottesville, VA, USADepartment of Electrical and Computer Engineering, University of Virginia, Charlottesville, VA, USADepartment of Electrical and Computer Engineering, University of Virginia, Charlottesville, VA, USAThis article presents a binary frequency-shift keying (BFSK) heterodyne wake-up receiver (WuRx) with -102-dBm sensitivity at 2.4 GHz. An integrated low-power all-digital phase-locked loop (ADPLL) allows sharp filtering at the intermediate frequency (IF) to improve sensitivity and interference robustness. The WuRx achieves an average current consumption of 2.2–<inline-formula> <tex-math notation="LaTeX">$171~\mu $ </tex-math></inline-formula>A range at 16 s to 0.1-s latency with the packet-level-duty-cycling scheme. In addition, it supports up to 60 channels from 2.300 to 2.536 GHz. A signal-to-interference ratio (SIR) of -27/-30/-46 dB is achieved at 3/5/25-MHz offset from the carrier.https://ieeexplore.ieee.org/document/10496457/All-digital phase-locked loop (ADPLL)Internet of Things (IoT)low powerreceiverswake-up radioswake-up receiver (WuRx) |
| spellingShingle | Linsheng Zhang Divya Duvvuri Suprio Bhattacharya Anjana Dissanayake Xinjian Liu Henry L. Bishop Yaobin Zhang Travis N. Blalock Benton H. Calhoun Steven M. Bowers A–102-dBm Sensitivity Multichannel Heterodyne Wake-Up Receiver With Integrated ADPLL IEEE Open Journal of the Solid-State Circuits Society All-digital phase-locked loop (ADPLL) Internet of Things (IoT) low power receivers wake-up radios wake-up receiver (WuRx) |
| title | A–102-dBm Sensitivity Multichannel Heterodyne Wake-Up Receiver With Integrated ADPLL |
| title_full | A–102-dBm Sensitivity Multichannel Heterodyne Wake-Up Receiver With Integrated ADPLL |
| title_fullStr | A–102-dBm Sensitivity Multichannel Heterodyne Wake-Up Receiver With Integrated ADPLL |
| title_full_unstemmed | A–102-dBm Sensitivity Multichannel Heterodyne Wake-Up Receiver With Integrated ADPLL |
| title_short | A–102-dBm Sensitivity Multichannel Heterodyne Wake-Up Receiver With Integrated ADPLL |
| title_sort | a x2013 102 dbm sensitivity multichannel heterodyne wake up receiver with integrated adpll |
| topic | All-digital phase-locked loop (ADPLL) Internet of Things (IoT) low power receivers wake-up radios wake-up receiver (WuRx) |
| url | https://ieeexplore.ieee.org/document/10496457/ |
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