A Cross-Scale Electrothermal Co-Simulation Approach for Power MOSFETs at Device–Package–Heatsink–Board Levels
This paper proposes a cross-scale simulation approach for evaluating the steady-state electrothermal performance of power MOSFETs at the device–package–heatsink–board (DPHB) level. A co-simulation framework is designed by employing the iterative process of power loss and chip temperature to bridge t...
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MDPI AG
2024-10-01
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| Online Access: | https://www.mdpi.com/2072-666X/15/11/1336 |
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| author | Yuxuan Dai Jiafei Yao Jing Chen Qingyou Qian Maolin Zhang Jun Zhang Qing Yao Chenyang Huang Mingshun Sun Yufeng Guo |
| author_facet | Yuxuan Dai Jiafei Yao Jing Chen Qingyou Qian Maolin Zhang Jun Zhang Qing Yao Chenyang Huang Mingshun Sun Yufeng Guo |
| author_sort | Yuxuan Dai |
| collection | DOAJ |
| description | This paper proposes a cross-scale simulation approach for evaluating the steady-state electrothermal performance of power MOSFETs at the device–package–heatsink–board (DPHB) level. A co-simulation framework is designed by employing the iterative process of power loss and chip temperature to bridge the device and package–heatsink–board (PHB) level simulators. As a result, the cross-scale electrothermal coupling effect within multilevel settings is considered. Correspondingly, variation values in chip temperature and temperature-dependent drain current can be obtained at various voltage biases, level settings, and DPHB structural parameters, incorporating cross-level physical insights. The simulation results are compared with existing methods, and their features and limitations are discussed. Additionally, this paper also derives an empirical equation from the co-simulations to characterize the relationship between the drain current and the chip temperature under different operations exactly. A commercial MOSFET with TO-220F packaging is implemented in experiments to extract the chip temperature and drain current in electrothermal equilibrium. The method comparisons and fair agreement among simulations, equations, and measurements presents the proposed approach as generalized and powerful for describing variations in chip temperature and drain current considering from micrometer devices to millimeter packages–heatsinks–PCB boards, thus providing effective support for DPHB-level co-design. |
| format | Article |
| id | doaj-art-436cccede56943108ec36de346c7eb3d |
| institution | OA Journals |
| issn | 2072-666X |
| language | English |
| publishDate | 2024-10-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Micromachines |
| spelling | doaj-art-436cccede56943108ec36de346c7eb3d2025-08-20T02:04:59ZengMDPI AGMicromachines2072-666X2024-10-011511133610.3390/mi15111336A Cross-Scale Electrothermal Co-Simulation Approach for Power MOSFETs at Device–Package–Heatsink–Board LevelsYuxuan Dai0Jiafei Yao1Jing Chen2Qingyou Qian3Maolin Zhang4Jun Zhang5Qing Yao6Chenyang Huang7Mingshun Sun8Yufeng Guo9College of Integrated Circuit Science and Engineering, Nanjing University of Posts and Telecommunications, Nanjing 210023, ChinaCollege of Integrated Circuit Science and Engineering, Nanjing University of Posts and Telecommunications, Nanjing 210023, ChinaCollege of Integrated Circuit Science and Engineering, Nanjing University of Posts and Telecommunications, Nanjing 210023, ChinaJIEJIE Microelectronics Co., Ltd., Nantong 226200, ChinaCollege of Integrated Circuit Science and Engineering, Nanjing University of Posts and Telecommunications, Nanjing 210023, ChinaCollege of Integrated Circuit Science and Engineering, Nanjing University of Posts and Telecommunications, Nanjing 210023, ChinaCollege of Integrated Circuit Science and Engineering, Nanjing University of Posts and Telecommunications, Nanjing 210023, ChinaCollege of Integrated Circuit Science and Engineering, Nanjing University of Posts and Telecommunications, Nanjing 210023, ChinaJIEJIE Microelectronics Co., Ltd., Nantong 226200, ChinaCollege of Integrated Circuit Science and Engineering, Nanjing University of Posts and Telecommunications, Nanjing 210023, ChinaThis paper proposes a cross-scale simulation approach for evaluating the steady-state electrothermal performance of power MOSFETs at the device–package–heatsink–board (DPHB) level. A co-simulation framework is designed by employing the iterative process of power loss and chip temperature to bridge the device and package–heatsink–board (PHB) level simulators. As a result, the cross-scale electrothermal coupling effect within multilevel settings is considered. Correspondingly, variation values in chip temperature and temperature-dependent drain current can be obtained at various voltage biases, level settings, and DPHB structural parameters, incorporating cross-level physical insights. The simulation results are compared with existing methods, and their features and limitations are discussed. Additionally, this paper also derives an empirical equation from the co-simulations to characterize the relationship between the drain current and the chip temperature under different operations exactly. A commercial MOSFET with TO-220F packaging is implemented in experiments to extract the chip temperature and drain current in electrothermal equilibrium. The method comparisons and fair agreement among simulations, equations, and measurements presents the proposed approach as generalized and powerful for describing variations in chip temperature and drain current considering from micrometer devices to millimeter packages–heatsinks–PCB boards, thus providing effective support for DPHB-level co-design.https://www.mdpi.com/2072-666X/15/11/1336chip temperaturedrain currentdevice–package–heatsink–board levelelectrothermal co-simulationpower MOSFETs |
| spellingShingle | Yuxuan Dai Jiafei Yao Jing Chen Qingyou Qian Maolin Zhang Jun Zhang Qing Yao Chenyang Huang Mingshun Sun Yufeng Guo A Cross-Scale Electrothermal Co-Simulation Approach for Power MOSFETs at Device–Package–Heatsink–Board Levels Micromachines chip temperature drain current device–package–heatsink–board level electrothermal co-simulation power MOSFETs |
| title | A Cross-Scale Electrothermal Co-Simulation Approach for Power MOSFETs at Device–Package–Heatsink–Board Levels |
| title_full | A Cross-Scale Electrothermal Co-Simulation Approach for Power MOSFETs at Device–Package–Heatsink–Board Levels |
| title_fullStr | A Cross-Scale Electrothermal Co-Simulation Approach for Power MOSFETs at Device–Package–Heatsink–Board Levels |
| title_full_unstemmed | A Cross-Scale Electrothermal Co-Simulation Approach for Power MOSFETs at Device–Package–Heatsink–Board Levels |
| title_short | A Cross-Scale Electrothermal Co-Simulation Approach for Power MOSFETs at Device–Package–Heatsink–Board Levels |
| title_sort | cross scale electrothermal co simulation approach for power mosfets at device package heatsink board levels |
| topic | chip temperature drain current device–package–heatsink–board level electrothermal co-simulation power MOSFETs |
| url | https://www.mdpi.com/2072-666X/15/11/1336 |
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