Synthesis of symmetric paths of arbiter physically unclonable function on FPGA
Physical cryptography is one of the current trends among the existing methods of protecting digital devices from illegal access. Circuit design solutions in physical cryptography are called digital physically unclonable functions (PUFs), which to be implemented ensure the uniqueness, non-reproducibi...
Saved in:
| Main Author: | |
|---|---|
| Format: | Article |
| Language: | Russian |
| Published: |
National Academy of Sciences of Belarus, the United Institute of Informatics Problems
2019-06-01
|
| Series: | Informatika |
| Subjects: | |
| Online Access: | https://inf.grid.by/jour/article/view/750 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| _version_ | 1832543144738029568 |
|---|---|
| author | A. A. Ivaniuk |
| author_facet | A. A. Ivaniuk |
| author_sort | A. A. Ivaniuk |
| collection | DOAJ |
| description | Physical cryptography is one of the current trends among the existing methods of protecting digital devices from illegal access. Circuit design solutions in physical cryptography are called digital physically unclonable functions (PUFs), which to be implemented ensure the uniqueness, non-reproducibility (non-cloning) of the protected digital device. In addition, PUFs should be efficient as hardware resources. The existing implementations of the arbiter PUF are based on the synthesis of configurable symmetric paths, when each link is a pair of two-input multiplexers providing two configurations of test signal translation: direct and cross. In order to build a single link on FPGA, it is necessary to use two built-in LUT-blocks, providing the implementation of two multiplexers, meanwhile the hardware resources of LUT-blocks are not fully utilized. The article presents a new architecture of symmetric paths of the arbiter PUF, allowing efficient use of hardware resources of LUT-blocks for various FPGA families. |
| format | Article |
| id | doaj-art-4292cf33a57a4cfdaac59290582d5b8c |
| institution | Kabale University |
| issn | 1816-0301 |
| language | Russian |
| publishDate | 2019-06-01 |
| publisher | National Academy of Sciences of Belarus, the United Institute of Informatics Problems |
| record_format | Article |
| series | Informatika |
| spelling | doaj-art-4292cf33a57a4cfdaac59290582d5b8c2025-02-03T11:51:48ZrusNational Academy of Sciences of Belarus, the United Institute of Informatics ProblemsInformatika1816-03012019-06-0116299108835Synthesis of symmetric paths of arbiter physically unclonable function on FPGAA. A. Ivaniuk0Belarusian State University of Informatics and RadioelectronicsPhysical cryptography is one of the current trends among the existing methods of protecting digital devices from illegal access. Circuit design solutions in physical cryptography are called digital physically unclonable functions (PUFs), which to be implemented ensure the uniqueness, non-reproducibility (non-cloning) of the protected digital device. In addition, PUFs should be efficient as hardware resources. The existing implementations of the arbiter PUF are based on the synthesis of configurable symmetric paths, when each link is a pair of two-input multiplexers providing two configurations of test signal translation: direct and cross. In order to build a single link on FPGA, it is necessary to use two built-in LUT-blocks, providing the implementation of two multiplexers, meanwhile the hardware resources of LUT-blocks are not fully utilized. The article presents a new architecture of symmetric paths of the arbiter PUF, allowing efficient use of hardware resources of LUT-blocks for various FPGA families.https://inf.grid.by/jour/article/view/750physically unclonable functionarbitersymmetrical pathsfpgalut-block |
| spellingShingle | A. A. Ivaniuk Synthesis of symmetric paths of arbiter physically unclonable function on FPGA Informatika physically unclonable function arbiter symmetrical paths fpga lut-block |
| title | Synthesis of symmetric paths of arbiter physically unclonable function on FPGA |
| title_full | Synthesis of symmetric paths of arbiter physically unclonable function on FPGA |
| title_fullStr | Synthesis of symmetric paths of arbiter physically unclonable function on FPGA |
| title_full_unstemmed | Synthesis of symmetric paths of arbiter physically unclonable function on FPGA |
| title_short | Synthesis of symmetric paths of arbiter physically unclonable function on FPGA |
| title_sort | synthesis of symmetric paths of arbiter physically unclonable function on fpga |
| topic | physically unclonable function arbiter symmetrical paths fpga lut-block |
| url | https://inf.grid.by/jour/article/view/750 |
| work_keys_str_mv | AT aaivaniuk synthesisofsymmetricpathsofarbiterphysicallyunclonablefunctiononfpga |