Controllable floating gate memory performance through device structure design
Floating gate memory devices based on two-dimensional materials hold tremendous potential for high-performance nonvolatile memory. However, the memory performance of the devices utilizing the same two-dimensional heterostructures exhibits significant differences from lab to lab, which is often attri...
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| Format: | Article |
| Language: | English |
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Elsevier
2025-12-01
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| Series: | Chip |
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| Online Access: | http://www.sciencedirect.com/science/article/pii/S2709472325000255 |
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| author | Ruitong Bie Ce Li Zirui Zhang Tianze Yu Dongliang Yang Binghe Liu Linfeng Sun |
| author_facet | Ruitong Bie Ce Li Zirui Zhang Tianze Yu Dongliang Yang Binghe Liu Linfeng Sun |
| author_sort | Ruitong Bie |
| collection | DOAJ |
| description | Floating gate memory devices based on two-dimensional materials hold tremendous potential for high-performance nonvolatile memory. However, the memory performance of the devices utilizing the same two-dimensional heterostructures exhibits significant differences from lab to lab, which is often attributed to variations in material thickness or interface quality without a detailed exploration. Such uncontrollable performance coupled with an insufficient understanding of the underlying working mechanism hinders the advancement of high-performance floating gate memory. Here, we report controllable and stable memory performance in floating gate memory devices through device structure design under precisely identical conditions. For the first time, the general differences in polarity and on/off ratio of the memory window caused by distinct structural features have been revealed and the underlying working mechanisms were clearly elucidated. Moreover, controllable tunneling paths that are responsible for two-terminal memory performance have also been demonstrated. The findings provide a general and reliable strategy for polarity control and performance optimization of two-dimensional floating gate memory devices. |
| format | Article |
| id | doaj-art-419b74d11cc44d7bb29fbcbc1c81e260 |
| institution | Kabale University |
| issn | 2709-4723 |
| language | English |
| publishDate | 2025-12-01 |
| publisher | Elsevier |
| record_format | Article |
| series | Chip |
| spelling | doaj-art-419b74d11cc44d7bb29fbcbc1c81e2602025-08-24T05:15:06ZengElsevierChip2709-47232025-12-014410015110.1016/j.chip.2025.100151Controllable floating gate memory performance through device structure designRuitong Bie0Ce Li1Zirui Zhang2Tianze Yu3Dongliang Yang4Binghe Liu5Linfeng Sun6Centre for Quantum Physics, Key Laboratory of Advanced Optoelectronic Quantum Architecture and Measurement (MOE), School of Physics, Beijing Institute of Technology, Beijing 100081, China; Beijing Key Lab of Nanophotonics & Ultrafine Optoelectronic Systems, School of Physics, Beijing Institute of Technology, Beijing 100081, ChinaCentre for Quantum Physics, Key Laboratory of Advanced Optoelectronic Quantum Architecture and Measurement (MOE), School of Physics, Beijing Institute of Technology, Beijing 100081, China; Beijing Key Lab of Nanophotonics & Ultrafine Optoelectronic Systems, School of Physics, Beijing Institute of Technology, Beijing 100081, ChinaCentre for Quantum Physics, Key Laboratory of Advanced Optoelectronic Quantum Architecture and Measurement (MOE), School of Physics, Beijing Institute of Technology, Beijing 100081, China; Beijing Key Lab of Nanophotonics & Ultrafine Optoelectronic Systems, School of Physics, Beijing Institute of Technology, Beijing 100081, ChinaCentre for Quantum Physics, Key Laboratory of Advanced Optoelectronic Quantum Architecture and Measurement (MOE), School of Physics, Beijing Institute of Technology, Beijing 100081, China; Beijing Key Lab of Nanophotonics & Ultrafine Optoelectronic Systems, School of Physics, Beijing Institute of Technology, Beijing 100081, ChinaCentre for Quantum Physics, Key Laboratory of Advanced Optoelectronic Quantum Architecture and Measurement (MOE), School of Physics, Beijing Institute of Technology, Beijing 100081, China; Beijing Key Lab of Nanophotonics & Ultrafine Optoelectronic Systems, School of Physics, Beijing Institute of Technology, Beijing 100081, ChinaCentre for Quantum Physics, Key Laboratory of Advanced Optoelectronic Quantum Architecture and Measurement (MOE), School of Physics, Beijing Institute of Technology, Beijing 100081, China; Beijing Key Lab of Nanophotonics & Ultrafine Optoelectronic Systems, School of Physics, Beijing Institute of Technology, Beijing 100081, ChinaCentre for Quantum Physics, Key Laboratory of Advanced Optoelectronic Quantum Architecture and Measurement (MOE), School of Physics, Beijing Institute of Technology, Beijing 100081, China; Beijing Key Lab of Nanophotonics & Ultrafine Optoelectronic Systems, School of Physics, Beijing Institute of Technology, Beijing 100081, China; Corresponding author.Floating gate memory devices based on two-dimensional materials hold tremendous potential for high-performance nonvolatile memory. However, the memory performance of the devices utilizing the same two-dimensional heterostructures exhibits significant differences from lab to lab, which is often attributed to variations in material thickness or interface quality without a detailed exploration. Such uncontrollable performance coupled with an insufficient understanding of the underlying working mechanism hinders the advancement of high-performance floating gate memory. Here, we report controllable and stable memory performance in floating gate memory devices through device structure design under precisely identical conditions. For the first time, the general differences in polarity and on/off ratio of the memory window caused by distinct structural features have been revealed and the underlying working mechanisms were clearly elucidated. Moreover, controllable tunneling paths that are responsible for two-terminal memory performance have also been demonstrated. The findings provide a general and reliable strategy for polarity control and performance optimization of two-dimensional floating gate memory devices.http://www.sciencedirect.com/science/article/pii/S2709472325000255Two-dimensional materialsvan der Waals heterostructureFloating gate memoryControllable memory performanceDevice structure design |
| spellingShingle | Ruitong Bie Ce Li Zirui Zhang Tianze Yu Dongliang Yang Binghe Liu Linfeng Sun Controllable floating gate memory performance through device structure design Chip Two-dimensional materials van der Waals heterostructure Floating gate memory Controllable memory performance Device structure design |
| title | Controllable floating gate memory performance through device structure design |
| title_full | Controllable floating gate memory performance through device structure design |
| title_fullStr | Controllable floating gate memory performance through device structure design |
| title_full_unstemmed | Controllable floating gate memory performance through device structure design |
| title_short | Controllable floating gate memory performance through device structure design |
| title_sort | controllable floating gate memory performance through device structure design |
| topic | Two-dimensional materials van der Waals heterostructure Floating gate memory Controllable memory performance Device structure design |
| url | http://www.sciencedirect.com/science/article/pii/S2709472325000255 |
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