Learning to rank quantum circuits for hardware-optimized performance enhancement
We introduce and experimentally test a machine-learning-based method for ranking logically equivalent quantum circuits based on expected performance estimates derived from a training procedure conducted on real hardware. We apply our method to the problem of layout selection, in which abstracted qub...
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| Format: | Article |
| Language: | English |
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Verein zur Förderung des Open Access Publizierens in den Quantenwissenschaften
2024-11-01
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| Series: | Quantum |
| Online Access: | https://quantum-journal.org/papers/q-2024-11-27-1542/pdf/ |
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| _version_ | 1850224743573094400 |
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| author | Gavin S. Hartnett Aaron Barbosa Pranav S. Mundada Michael Hush Michael J. Biercuk Yuval Baum |
| author_facet | Gavin S. Hartnett Aaron Barbosa Pranav S. Mundada Michael Hush Michael J. Biercuk Yuval Baum |
| author_sort | Gavin S. Hartnett |
| collection | DOAJ |
| description | We introduce and experimentally test a machine-learning-based method for ranking logically equivalent quantum circuits based on expected performance estimates derived from a training procedure conducted on real hardware. We apply our method to the problem of layout selection, in which abstracted qubits are assigned to physical qubits on a given device. Circuit measurements performed on IBM hardware indicate that the maximum and median fidelities of logically equivalent layouts can differ by an order of magnitude. We introduce a circuit score used for ranking that is parameterized in terms of a physics-based, phenomenological error model whose parameters are fit by training a ranking-loss function over a measured dataset. The dataset consists of quantum circuits exhibiting a diversity of structures and executed on IBM hardware, allowing the model to incorporate the contextual nature of real device noise and errors without the need to perform an exponentially costly tomographic protocol. We perform model training and execution on the 16-qubit $ibmq\_guadalupe$ device and compare our method to two common approaches: random layout selection and a publicly available baseline called Mapomatic. Our model consistently outperforms both approaches, predicting layouts that exhibit lower noise and higher performance. In particular, we find that our best model leads to a $1.8\times$ reduction in selection error when compared to the baseline approach and a $3.2\times$ reduction when compared to random selection. Beyond delivering a new form of predictive quantum characterization, verification, and validation, our results reveal the specific way in which context-dependent and coherent gate errors appear to dominate the divergence from performance estimates extrapolated from simple proxy measures. |
| format | Article |
| id | doaj-art-3f9d0b3d3acb489b9dd67d22c6306649 |
| institution | OA Journals |
| issn | 2521-327X |
| language | English |
| publishDate | 2024-11-01 |
| publisher | Verein zur Förderung des Open Access Publizierens in den Quantenwissenschaften |
| record_format | Article |
| series | Quantum |
| spelling | doaj-art-3f9d0b3d3acb489b9dd67d22c63066492025-08-20T02:05:32ZengVerein zur Förderung des Open Access Publizierens in den QuantenwissenschaftenQuantum2521-327X2024-11-018154210.22331/q-2024-11-27-154210.22331/q-2024-11-27-1542Learning to rank quantum circuits for hardware-optimized performance enhancementGavin S. HartnettAaron BarbosaPranav S. MundadaMichael HushMichael J. BiercukYuval BaumWe introduce and experimentally test a machine-learning-based method for ranking logically equivalent quantum circuits based on expected performance estimates derived from a training procedure conducted on real hardware. We apply our method to the problem of layout selection, in which abstracted qubits are assigned to physical qubits on a given device. Circuit measurements performed on IBM hardware indicate that the maximum and median fidelities of logically equivalent layouts can differ by an order of magnitude. We introduce a circuit score used for ranking that is parameterized in terms of a physics-based, phenomenological error model whose parameters are fit by training a ranking-loss function over a measured dataset. The dataset consists of quantum circuits exhibiting a diversity of structures and executed on IBM hardware, allowing the model to incorporate the contextual nature of real device noise and errors without the need to perform an exponentially costly tomographic protocol. We perform model training and execution on the 16-qubit $ibmq\_guadalupe$ device and compare our method to two common approaches: random layout selection and a publicly available baseline called Mapomatic. Our model consistently outperforms both approaches, predicting layouts that exhibit lower noise and higher performance. In particular, we find that our best model leads to a $1.8\times$ reduction in selection error when compared to the baseline approach and a $3.2\times$ reduction when compared to random selection. Beyond delivering a new form of predictive quantum characterization, verification, and validation, our results reveal the specific way in which context-dependent and coherent gate errors appear to dominate the divergence from performance estimates extrapolated from simple proxy measures.https://quantum-journal.org/papers/q-2024-11-27-1542/pdf/ |
| spellingShingle | Gavin S. Hartnett Aaron Barbosa Pranav S. Mundada Michael Hush Michael J. Biercuk Yuval Baum Learning to rank quantum circuits for hardware-optimized performance enhancement Quantum |
| title | Learning to rank quantum circuits for hardware-optimized performance enhancement |
| title_full | Learning to rank quantum circuits for hardware-optimized performance enhancement |
| title_fullStr | Learning to rank quantum circuits for hardware-optimized performance enhancement |
| title_full_unstemmed | Learning to rank quantum circuits for hardware-optimized performance enhancement |
| title_short | Learning to rank quantum circuits for hardware-optimized performance enhancement |
| title_sort | learning to rank quantum circuits for hardware optimized performance enhancement |
| url | https://quantum-journal.org/papers/q-2024-11-27-1542/pdf/ |
| work_keys_str_mv | AT gavinshartnett learningtorankquantumcircuitsforhardwareoptimizedperformanceenhancement AT aaronbarbosa learningtorankquantumcircuitsforhardwareoptimizedperformanceenhancement AT pranavsmundada learningtorankquantumcircuitsforhardwareoptimizedperformanceenhancement AT michaelhush learningtorankquantumcircuitsforhardwareoptimizedperformanceenhancement AT michaeljbiercuk learningtorankquantumcircuitsforhardwareoptimizedperformanceenhancement AT yuvalbaum learningtorankquantumcircuitsforhardwareoptimizedperformanceenhancement |