Two Dimensional Modeling of III-V Heterojunction Gate All Around Tunnel Field Effect Transistor
Tunnel Field Effect Transistor is one of the extensively researched semiconductor devices, which has captured attention over the conventional Metal Oxide Semiconductor Field Effect Transistor. This device, due to its varied advantages, is considered in applications where devices are scaled down to d...
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| Format: | Article |
| Language: | English |
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Sumy State University
2017-02-01
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| Series: | Журнал нано- та електронної фізики |
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| Online Access: | http://jnep.sumdu.edu.ua/download/numbers/2017/1/articles/jnep_V9_01030.pdf |
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| author | Manjula Vijh R.S. Gupta Sujata Pandey |
| author_facet | Manjula Vijh R.S. Gupta Sujata Pandey |
| author_sort | Manjula Vijh |
| collection | DOAJ |
| description | Tunnel Field Effect Transistor is one of the extensively researched semiconductor devices, which has captured attention over the conventional Metal Oxide Semiconductor Field Effect Transistor. This device, due to its varied advantages, is considered in applications where devices are scaled down to deep sub-micron level. Like MOSFETs, many geometries of TFETs have been studied and analyzed in the past few years. This work, presents a two dimensional analytical model for a III-V Heterojunction Surrounding Gate Tunneling Field Effect Transistor. 2-D Poisson’s equation in cylindrical coordinates has been solved to derive the expression of Surface Potential and threshold voltage of the device. A broken gap GaSb/InAs heterostructure has been considered in this work. Variation of potential profiles are shown with different gate and drain biases, by varying radius of the transistor,and different gate metals. Also, variation of threshold voltage is shown with respect to channel length and radius of the nanowire. |
| format | Article |
| id | doaj-art-3f722b3e37ea47108c083bb768859dc1 |
| institution | OA Journals |
| issn | 2077-6772 |
| language | English |
| publishDate | 2017-02-01 |
| publisher | Sumy State University |
| record_format | Article |
| series | Журнал нано- та електронної фізики |
| spelling | doaj-art-3f722b3e37ea47108c083bb768859dc12025-08-20T01:56:20ZengSumy State UniversityЖурнал нано- та електронної фізики2077-67722017-02-019101030-101030-410.21272/jnep.9(1).01030Two Dimensional Modeling of III-V Heterojunction Gate All Around Tunnel Field Effect TransistorManjula Vijh0R.S. Gupta1Sujata Pandey2Amity University Uttar Pradesh, Noida, IndiaMaharaja Agrasen Institute of Technology, New Delhi, IndiaAmity Institute of Telecom Engineering and Management, Amity University Uttar Pradesh, Noida, IndiaTunnel Field Effect Transistor is one of the extensively researched semiconductor devices, which has captured attention over the conventional Metal Oxide Semiconductor Field Effect Transistor. This device, due to its varied advantages, is considered in applications where devices are scaled down to deep sub-micron level. Like MOSFETs, many geometries of TFETs have been studied and analyzed in the past few years. This work, presents a two dimensional analytical model for a III-V Heterojunction Surrounding Gate Tunneling Field Effect Transistor. 2-D Poisson’s equation in cylindrical coordinates has been solved to derive the expression of Surface Potential and threshold voltage of the device. A broken gap GaSb/InAs heterostructure has been considered in this work. Variation of potential profiles are shown with different gate and drain biases, by varying radius of the transistor,and different gate metals. Also, variation of threshold voltage is shown with respect to channel length and radius of the nanowire.http://jnep.sumdu.edu.ua/download/numbers/2017/1/articles/jnep_V9_01030.pdfSurrounding gate Tunnel FETHeterojunctionSurface PotentialThreshold VoltageBroken-ga |
| spellingShingle | Manjula Vijh R.S. Gupta Sujata Pandey Two Dimensional Modeling of III-V Heterojunction Gate All Around Tunnel Field Effect Transistor Журнал нано- та електронної фізики Surrounding gate Tunnel FET Heterojunction Surface Potential Threshold Voltage Broken-ga |
| title | Two Dimensional Modeling of III-V Heterojunction Gate All Around Tunnel Field Effect Transistor |
| title_full | Two Dimensional Modeling of III-V Heterojunction Gate All Around Tunnel Field Effect Transistor |
| title_fullStr | Two Dimensional Modeling of III-V Heterojunction Gate All Around Tunnel Field Effect Transistor |
| title_full_unstemmed | Two Dimensional Modeling of III-V Heterojunction Gate All Around Tunnel Field Effect Transistor |
| title_short | Two Dimensional Modeling of III-V Heterojunction Gate All Around Tunnel Field Effect Transistor |
| title_sort | two dimensional modeling of iii v heterojunction gate all around tunnel field effect transistor |
| topic | Surrounding gate Tunnel FET Heterojunction Surface Potential Threshold Voltage Broken-ga |
| url | http://jnep.sumdu.edu.ua/download/numbers/2017/1/articles/jnep_V9_01030.pdf |
| work_keys_str_mv | AT manjulavijh twodimensionalmodelingofiiivheterojunctiongateallaroundtunnelfieldeffecttransistor AT rsgupta twodimensionalmodelingofiiivheterojunctiongateallaroundtunnelfieldeffecttransistor AT sujatapandey twodimensionalmodelingofiiivheterojunctiongateallaroundtunnelfieldeffecttransistor |