Accelerating the SM3 hash algorithm with CPU‐FPGA Co‐Designed architecture
Abstract SM3 hash algorithm developed by the Chinese Government is used in various fields of information security, and it is being widely used in commercial security products. However, the performance of implementation on the software architecture is not sufficient for high‐speed applications. This...
Saved in:
Main Authors: | Xiaoying Huang, Zhichuan Guo, Mangu Song, Xuewen Zeng |
---|---|
Format: | Article |
Language: | English |
Published: |
Wiley
2021-11-01
|
Series: | IET Computers & Digital Techniques |
Subjects: | |
Online Access: | https://doi.org/10.1049/cdt2.12034 |
Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Similar Items
-
Performance evaluation of the SM4 cipher based on field‐programmable gate array implementation
by: Sa'ed Abed, et al.
Published: (2021-03-01) -
Efficient FPGA based architecture for high‐order FIR filtering using simultaneous DSP and LUT reduced utilization
by: Mountassar Maamoun, et al.
Published: (2021-08-01) -
Portable and Cost-Effective Handheld Ultrasound System Utilizing FPGA-Based Synthetic Aperture Imaging
by: Wenping Wang, et al.
Published: (2024-01-01) -
Strengthened 32‐bit AES implementation: Architectural error correction configuration with a new voting scheme
by: Saeideh Sheikhpur, et al.
Published: (2021-11-01) -
Blinding HT: Hiding Hardware Trojan signals traced across multiple sequential levels
by: Ying Zhang, et al.
Published: (2022-01-01)