Millimeter-Wave All-Digital Phase-Locked Loop Using Reference Waveform Oversampling Techniques

Millimeter-Wave All-Digital Phase-Locked Loop Using Reference Waveform Oversampling Techniques

This article proposes an mm-wave fractional-N all-digital phase-locked loop (ADPLL) employing a reference-waveform oversampling (ROS) phase detector (PD) that increases its effective rate four times, consequently improving jitter at lower power consumption while using a low-frequency reference of 50...

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Bibliographic Details
Main Authors: Teerachot Siriburanon, Chunxiao Liu, Jianglin Du, Robert Bogdan Staszewski
Format: Article
Language:English
Published: IEEE 2024-01-01
Series:IEEE Open Journal of the Solid-State Circuits Society
Subjects:
All-digital phase-locked loop (ADPLL)
fractional-N
low jitter
low power
millimeter-wave (mmW)
reference-sampling PLL (RS-PLL)
Online Access:https://ieeexplore.ieee.org/document/10746550/
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Summary:This article proposes an mm-wave fractional-N all-digital phase-locked loop (ADPLL) employing a reference-waveform oversampling (ROS) phase detector (PD) that increases its effective rate four times, consequently improving jitter at lower power consumption while using a low-frequency reference of 50 MHz. The passive oversampling PD utilizes a zero-forcing technique for voltage-domain presetting and compensation for both the fractional phase and reference spurs induced by imperfections in the reference waveform and reference-waveform oversampling PD (ROS-PD). The ROS-PD eliminates the conventional power-hungry low-noise buffer for the reference input and reduces the PD noise by increasing the loop correction speed. This promotes low jitter and high efficiency in advanced mm-wave PLLs without relying on the increase of the reference clock frequency to several hundred MHz. The imperfections in the reference waveform and ROS-PD, i.e., harmonic distortion, differential path mismatches, and other nonideality factors, can be programmably compensated by the proposed digital manifold calibration scheme, resulting in low reference spurs. A class-F3 oscillator is used to generate a ~10-GHz signal for the feedback divider along with its third harmonic for the harmonic extractor to generate the ~30-GHz output. The proposed ADPLL is implemented in TSMC 28-nm LP CMOS. The prototype generates a 24&#x2013;31-GHz output carrier with rms jitter of 237 fs while consuming only 12 mW. This corresponds to a state-of-the-art ADPLL <inline-formula> <tex-math notation="LaTeX">${\mathrm {FoM}}_{\text {jitter-N}}$ </tex-math></inline-formula> of &#x2212;269 dB in a fractional-N mode. Using a comprehensive digital calibration, the reference spurious tones can be reduced from &#x2212;33 to &#x2212;65 dBc.
ISSN:2644-1349

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