URcon: Unified and Reconfigurable Control and Verification Platform for Multi-Mode Customized eDRAM and SRAM Macros
With the rapid development of various technologies, processing large amounts of data has become essential. To address this trend, various high-density and high-performance memories have emerged. However, they employ different operation modes and architectures, necessitating the redesign of the contr...
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| Main Authors: | , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
IEEE
2025-01-01
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| Series: | IEEE Access |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/10896669/ |
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| Summary: | With the rapid development of various technologies, processing large amounts of data has become essential. To address this trend, various high-density and high-performance memories have emerged. However, they employ different operation modes and architectures, necessitating the redesign of the control and verification platforms each time a new memory type is supported. To solve this problem, we propose a unified and reconfigurable platform to support the control and verification of various memories, each with different structures and operational modes. Some of the control and verification functions are integrated into the chip as a unified memory command controller (UMCC) to alleviate the limitations posed by the finite number of I/O pads. Other control and verification functions are implemented on a field-programmable gate array (FPGA) to support various memory operations and testing. Additionally, a software application has been used to manage the FPGA controller, enabling the flexible modification of input variables and enhancing the reconfigurability of the proposed platform. We designed prototype chips for customized 16-kb multi-mode embedded dynamic random-access memory (eDRAM) and static RAM (SRAM) macros using a 28-nm CMOS process. Their various operations and performances, such as data write, single- and multi-column data read, refresh, data retention time analysis, and power measurement, have been validated through the proposed platform. This platform can be extended and applied to verify other memories with minimal modifications. |
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| ISSN: | 2169-3536 |