A Chisel Generator for Standardized 3-D Die-to-Die Interconnects
A 3-D heterogeneous integration (3-D-HI) is poised to enable a new era of high-performance integrated circuits via a multitude of benefits, including a reduction in I/O power consumption and ability to tightly couple disparate technologies. However, a significant hurdle toward enabling a chiplet eco...
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IEEE
2024-01-01
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| Series: | IEEE Journal on Exploratory Solid-State Computational Devices and Circuits |
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| Online Access: | https://ieeexplore.ieee.org/document/10681023/ |
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| author | Harrison Liew Farhana Sheikh Jong-Ru Guo Zuoguo Wu Borivoje Nikolic |
| author_facet | Harrison Liew Farhana Sheikh Jong-Ru Guo Zuoguo Wu Borivoje Nikolic |
| author_sort | Harrison Liew |
| collection | DOAJ |
| description | A 3-D heterogeneous integration (3-D-HI) is poised to enable a new era of high-performance integrated circuits via a multitude of benefits, including a reduction in I/O power consumption and ability to tightly couple disparate technologies. However, a significant hurdle toward enabling a chiplet ecosystem is the standardization of 3-D die-to-die (D2D) interconnects that facilitate rapid integration. Technology-driven constraints highlighted in published works demonstrate that a unique approach to 3-D D2D interconnect design and implementation is required, while preserving the ability to customize the interconnect to accommodate future technology concerns and applications with minimal overhead. This article presents a framework to generate customized 3-D D2D interconnect physical layers (PHYs) that are simultaneously standard-compliant, physical-aware, and can be automatically integrated into all stacked chiplets. The generator framework leverages the Chisel hardware description language to allow designers to do the following: 1) compile a port list directly into a PHY; 2) automate design and physical design (PD); and 3) perform design space exploration of interconnect features (e.g., bump map pitch, clocking architecture, and others). The 3-D PHY generator framework and features detailed in this work can be used to produce a reference implementation for a standard like UCIe-3-D, representing a significant paradigm shift from current specification and design methodologies for 2.5-D D2D interconnect (e.g., UCIe) implementations. This work concludes with the results of a redundancy design space exploration tradeoff study, showing the benefits of a proposed spatial coding redundancy scheme in an example PHY using emulated 9-<inline-formula> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula>m hybrid bonding for a 4 Tx/4 Rx module array with 4:1 coding redundancy ratio. |
| format | Article |
| id | doaj-art-3e1afd9fa4854fc59e626099cfacaca5 |
| institution | Kabale University |
| issn | 2329-9231 |
| language | English |
| publishDate | 2024-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Journal on Exploratory Solid-State Computational Devices and Circuits |
| spelling | doaj-art-3e1afd9fa4854fc59e626099cfacaca52025-01-17T00:00:30ZengIEEEIEEE Journal on Exploratory Solid-State Computational Devices and Circuits2329-92312024-01-0110586610.1109/JXCDC.2024.346147110681023A Chisel Generator for Standardized 3-D Die-to-Die InterconnectsHarrison Liew0https://orcid.org/0000-0003-3600-3951Farhana Sheikh1https://orcid.org/0000-0001-5078-0816Jong-Ru Guo2https://orcid.org/0009-0007-7024-2434Zuoguo Wu3https://orcid.org/0009-0004-0878-963XBorivoje Nikolic4https://orcid.org/0000-0003-2324-1715Electrical Engineering and Computer Sciences Department, University of California at Berkeley, Berkeley, CA, USAIntel Corporation, Hillsboro, OR, USAIntel Corporation, Hillsboro, OR, USAIntel Corporation, Santa Clara, CA, USAElectrical Engineering and Computer Sciences Department, University of California at Berkeley, Berkeley, CA, USAA 3-D heterogeneous integration (3-D-HI) is poised to enable a new era of high-performance integrated circuits via a multitude of benefits, including a reduction in I/O power consumption and ability to tightly couple disparate technologies. However, a significant hurdle toward enabling a chiplet ecosystem is the standardization of 3-D die-to-die (D2D) interconnects that facilitate rapid integration. Technology-driven constraints highlighted in published works demonstrate that a unique approach to 3-D D2D interconnect design and implementation is required, while preserving the ability to customize the interconnect to accommodate future technology concerns and applications with minimal overhead. This article presents a framework to generate customized 3-D D2D interconnect physical layers (PHYs) that are simultaneously standard-compliant, physical-aware, and can be automatically integrated into all stacked chiplets. The generator framework leverages the Chisel hardware description language to allow designers to do the following: 1) compile a port list directly into a PHY; 2) automate design and physical design (PD); and 3) perform design space exploration of interconnect features (e.g., bump map pitch, clocking architecture, and others). The 3-D PHY generator framework and features detailed in this work can be used to produce a reference implementation for a standard like UCIe-3-D, representing a significant paradigm shift from current specification and design methodologies for 2.5-D D2D interconnect (e.g., UCIe) implementations. This work concludes with the results of a redundancy design space exploration tradeoff study, showing the benefits of a proposed spatial coding redundancy scheme in an example PHY using emulated 9-<inline-formula> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula>m hybrid bonding for a 4 Tx/4 Rx module array with 4:1 coding redundancy ratio.https://ieeexplore.ieee.org/document/10681023/3-D integrated circuitsdie-to-die (D2D) interconnectsgeneratorphysical design (PD)physical layer (PHY)redundancy |
| spellingShingle | Harrison Liew Farhana Sheikh Jong-Ru Guo Zuoguo Wu Borivoje Nikolic A Chisel Generator for Standardized 3-D Die-to-Die Interconnects IEEE Journal on Exploratory Solid-State Computational Devices and Circuits 3-D integrated circuits die-to-die (D2D) interconnects generator physical design (PD) physical layer (PHY) redundancy |
| title | A Chisel Generator for Standardized 3-D Die-to-Die Interconnects |
| title_full | A Chisel Generator for Standardized 3-D Die-to-Die Interconnects |
| title_fullStr | A Chisel Generator for Standardized 3-D Die-to-Die Interconnects |
| title_full_unstemmed | A Chisel Generator for Standardized 3-D Die-to-Die Interconnects |
| title_short | A Chisel Generator for Standardized 3-D Die-to-Die Interconnects |
| title_sort | chisel generator for standardized 3 d die to die interconnects |
| topic | 3-D integrated circuits die-to-die (D2D) interconnects generator physical design (PD) physical layer (PHY) redundancy |
| url | https://ieeexplore.ieee.org/document/10681023/ |
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