Novel NoC Topology Construction for High-Performance Communications
Different intellectual property (IP) cores, including processor and memory, are interconnected to build a typical system-on-chip (SoC) architecture. Larger SoC designs dictate the data communication to happen over the global interconnects. Network-on-Chip(NoC) architectures have been proposed as a s...
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| Format: | Article |
| Language: | English |
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Wiley
2011-01-01
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| Series: | Journal of Computer Networks and Communications |
| Online Access: | http://dx.doi.org/10.1155/2011/405697 |
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| author | P. Ezhumalai A. Chilambuchelvan C. Arun |
| author_facet | P. Ezhumalai A. Chilambuchelvan C. Arun |
| author_sort | P. Ezhumalai |
| collection | DOAJ |
| description | Different intellectual property (IP) cores, including processor and memory, are interconnected to build a typical system-on-chip (SoC) architecture. Larger SoC designs dictate the data communication to happen over the global interconnects. Network-on-Chip(NoC) architectures have been proposed as a scalable solution to the global communication challenges in nanoscale systems-on-chip (SoC) design. We proposed an idea on building customizing synthesis network—on-chip with the better flow partitioning and also considered power and area reduction as compared to the already presented regular topologies. Hence to improve the performance of SoC, first, we did a performance study of regular interconnect topologies MESH, TORUS, BFT and EBFT, we observed that the overall latency and throughput of the EBFT is better compared to other topologies, The next best in case of latency and throughput is BFT. Experimental results on a variety of NoC benchmarks showed that our synthesis results were achieved reduction in power consumption and average hop count over custom topology implementation. |
| format | Article |
| id | doaj-art-3aa93f5accc944c4a3d4d09dc1620d03 |
| institution | OA Journals |
| issn | 2090-7141 2090-715X |
| language | English |
| publishDate | 2011-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | Journal of Computer Networks and Communications |
| spelling | doaj-art-3aa93f5accc944c4a3d4d09dc1620d032025-08-20T02:07:47ZengWileyJournal of Computer Networks and Communications2090-71412090-715X2011-01-01201110.1155/2011/405697405697Novel NoC Topology Construction for High-Performance CommunicationsP. Ezhumalai0A. Chilambuchelvan1C. Arun2Department of Computer Science and Engineering, Rajalakshmi Engineering College, Thandalam Chennai 602 105, IndiaDepartment of Computer Science and Engineering, R.M.K Engineering College, Chennai 600 040, IndiaDepartment of Computer Science and Engineering, Rajalakshmi Engineering College, Thandalam Chennai 602 105, IndiaDifferent intellectual property (IP) cores, including processor and memory, are interconnected to build a typical system-on-chip (SoC) architecture. Larger SoC designs dictate the data communication to happen over the global interconnects. Network-on-Chip(NoC) architectures have been proposed as a scalable solution to the global communication challenges in nanoscale systems-on-chip (SoC) design. We proposed an idea on building customizing synthesis network—on-chip with the better flow partitioning and also considered power and area reduction as compared to the already presented regular topologies. Hence to improve the performance of SoC, first, we did a performance study of regular interconnect topologies MESH, TORUS, BFT and EBFT, we observed that the overall latency and throughput of the EBFT is better compared to other topologies, The next best in case of latency and throughput is BFT. Experimental results on a variety of NoC benchmarks showed that our synthesis results were achieved reduction in power consumption and average hop count over custom topology implementation.http://dx.doi.org/10.1155/2011/405697 |
| spellingShingle | P. Ezhumalai A. Chilambuchelvan C. Arun Novel NoC Topology Construction for High-Performance Communications Journal of Computer Networks and Communications |
| title | Novel NoC Topology Construction for High-Performance Communications |
| title_full | Novel NoC Topology Construction for High-Performance Communications |
| title_fullStr | Novel NoC Topology Construction for High-Performance Communications |
| title_full_unstemmed | Novel NoC Topology Construction for High-Performance Communications |
| title_short | Novel NoC Topology Construction for High-Performance Communications |
| title_sort | novel noc topology construction for high performance communications |
| url | http://dx.doi.org/10.1155/2011/405697 |
| work_keys_str_mv | AT pezhumalai novelnoctopologyconstructionforhighperformancecommunications AT achilambuchelvan novelnoctopologyconstructionforhighperformancecommunications AT carun novelnoctopologyconstructionforhighperformancecommunications |