Automatic Generation of Simulators for Processors Enhanced for Security in Virtualization
All new computer architectures need to be performance evaluated for acceptance and simulation is the most widely used method for evaluation of new processor designs. Sharing resources with virtualization raised many security concerns, leading to the development of processors that are enhanced for se...
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| Format: | Article |
| Language: | English |
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IEEE
2025-01-01
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| Series: | IEEE Access |
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| Online Access: | https://ieeexplore.ieee.org/document/10840183/ |
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| author | Swapneel C. Mhatre Priya Chandran |
| author_facet | Swapneel C. Mhatre Priya Chandran |
| author_sort | Swapneel C. Mhatre |
| collection | DOAJ |
| description | All new computer architectures need to be performance evaluated for acceptance and simulation is the most widely used method for evaluation of new processor designs. Sharing resources with virtualization raised many security concerns, leading to the development of processors that are enhanced for security in virtualization. The simulators for processors enhanced for security in virtualization need to perform simulation of hypervisor instructions, simulation of security in virtualization, and simulation of new instructions. However, a simulator with all of these three features is not found in the literature. Hence, this paper proposes an approach for the simulation of processors enhanced for security in virtualization that provides all these three features. For user convenience, the simulators are generated automatically from the target processor specifications using a simulator generator. The paper also proposes an approach for simulating a new pipeline with a designer-specified number of stages with automatic detection of pipeline hazards and automatic stalling or flushing of the pipeline on detection of hazards. To demonstrate the use of the simulator generator and the generated simulator, three case studies are considered - simulation of RISC-V with HyperWall, simulation of RISC-V with bit-serial dot-product unit, and simulation of RISC-V with Galois Field arithmetic extension. The paper concludes that the proposed approaches help in accurately simulating the overhead due to security in virtualization and also in providing flexibility to the designer to simulate the desired processor configurations. |
| format | Article |
| id | doaj-art-37e612d7f5494d0d8b790652fe216818 |
| institution | Kabale University |
| issn | 2169-3536 |
| language | English |
| publishDate | 2025-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj-art-37e612d7f5494d0d8b790652fe2168182025-01-24T00:01:18ZengIEEEIEEE Access2169-35362025-01-0113119301194310.1109/ACCESS.2025.352966710840183Automatic Generation of Simulators for Processors Enhanced for Security in VirtualizationSwapneel C. Mhatre0https://orcid.org/0000-0002-7809-3660Priya Chandran1Department of Computer Science and Engineering, National Institute of Technology Calicut, Kozhikode, Kerala, IndiaDepartment of Computer Science and Engineering, National Institute of Technology Calicut, Kozhikode, Kerala, IndiaAll new computer architectures need to be performance evaluated for acceptance and simulation is the most widely used method for evaluation of new processor designs. Sharing resources with virtualization raised many security concerns, leading to the development of processors that are enhanced for security in virtualization. The simulators for processors enhanced for security in virtualization need to perform simulation of hypervisor instructions, simulation of security in virtualization, and simulation of new instructions. However, a simulator with all of these three features is not found in the literature. Hence, this paper proposes an approach for the simulation of processors enhanced for security in virtualization that provides all these three features. For user convenience, the simulators are generated automatically from the target processor specifications using a simulator generator. The paper also proposes an approach for simulating a new pipeline with a designer-specified number of stages with automatic detection of pipeline hazards and automatic stalling or flushing of the pipeline on detection of hazards. To demonstrate the use of the simulator generator and the generated simulator, three case studies are considered - simulation of RISC-V with HyperWall, simulation of RISC-V with bit-serial dot-product unit, and simulation of RISC-V with Galois Field arithmetic extension. The paper concludes that the proposed approaches help in accurately simulating the overhead due to security in virtualization and also in providing flexibility to the designer to simulate the desired processor configurations.https://ieeexplore.ieee.org/document/10840183/Compilercomputer architecturehypervisoroperating systemsecurity in virtualizationsimulation |
| spellingShingle | Swapneel C. Mhatre Priya Chandran Automatic Generation of Simulators for Processors Enhanced for Security in Virtualization IEEE Access Compiler computer architecture hypervisor operating system security in virtualization simulation |
| title | Automatic Generation of Simulators for Processors Enhanced for Security in Virtualization |
| title_full | Automatic Generation of Simulators for Processors Enhanced for Security in Virtualization |
| title_fullStr | Automatic Generation of Simulators for Processors Enhanced for Security in Virtualization |
| title_full_unstemmed | Automatic Generation of Simulators for Processors Enhanced for Security in Virtualization |
| title_short | Automatic Generation of Simulators for Processors Enhanced for Security in Virtualization |
| title_sort | automatic generation of simulators for processors enhanced for security in virtualization |
| topic | Compiler computer architecture hypervisor operating system security in virtualization simulation |
| url | https://ieeexplore.ieee.org/document/10840183/ |
| work_keys_str_mv | AT swapneelcmhatre automaticgenerationofsimulatorsforprocessorsenhancedforsecurityinvirtualization AT priyachandran automaticgenerationofsimulatorsforprocessorsenhancedforsecurityinvirtualization |