RP-Ring: A Heterogeneous Multi-FPGA Accelerator
To reduce the cost of designing new specialized FPGA boards as direct-summation MOND (Modified Newtonian Dynamics) simulator, we propose a new heterogeneous architecture with existing FPGA boards, which is called RP-ring (reconfigurable processor ring). This design can be expanded conveniently with...
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| Main Authors: | , , , , , |
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| Format: | Article |
| Language: | English |
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Wiley
2018-01-01
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| Series: | International Journal of Reconfigurable Computing |
| Online Access: | http://dx.doi.org/10.1155/2018/6784319 |
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| _version_ | 1832567298513174528 |
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| author | Shuaizhi Guo Tianqi Wang Linfeng Tao Teng Tian Zikun Xiang Xi Jin |
| author_facet | Shuaizhi Guo Tianqi Wang Linfeng Tao Teng Tian Zikun Xiang Xi Jin |
| author_sort | Shuaizhi Guo |
| collection | DOAJ |
| description | To reduce the cost of designing new specialized FPGA boards as direct-summation MOND (Modified Newtonian Dynamics) simulator, we propose a new heterogeneous architecture with existing FPGA boards, which is called RP-ring (reconfigurable processor ring). This design can be expanded conveniently with any available FPGA board and only requires quite low communication bandwidth between FPGA boards. The communication protocol is simple and can be implemented with limited hardware/software resources. In order to avoid overall performance loss caused by the slowest board, we build a mathematical model to decompose workload among FPGAs. The dividing of workload is based on the logic resource, memory access bandwidth, and communication bandwidth of each FPGA chip. Our accelerator can achieve two orders of magnitude speedup compared with CPU implementation. |
| format | Article |
| id | doaj-art-364a7042e6c54466b0f1529012009793 |
| institution | Kabale University |
| issn | 1687-7195 1687-7209 |
| language | English |
| publishDate | 2018-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | International Journal of Reconfigurable Computing |
| spelling | doaj-art-364a7042e6c54466b0f15290120097932025-02-03T01:01:47ZengWileyInternational Journal of Reconfigurable Computing1687-71951687-72092018-01-01201810.1155/2018/67843196784319RP-Ring: A Heterogeneous Multi-FPGA AcceleratorShuaizhi Guo0Tianqi Wang1Linfeng Tao2Teng Tian3Zikun Xiang4Xi Jin5University of Science and Technology of China, Hefei, ChinaUniversity of Science and Technology of China, Hefei, ChinaUniversity of Science and Technology of China, Hefei, ChinaUniversity of Science and Technology of China, Hefei, ChinaUniversity of Science and Technology of China, Hefei, ChinaUniversity of Science and Technology of China, Hefei, ChinaTo reduce the cost of designing new specialized FPGA boards as direct-summation MOND (Modified Newtonian Dynamics) simulator, we propose a new heterogeneous architecture with existing FPGA boards, which is called RP-ring (reconfigurable processor ring). This design can be expanded conveniently with any available FPGA board and only requires quite low communication bandwidth between FPGA boards. The communication protocol is simple and can be implemented with limited hardware/software resources. In order to avoid overall performance loss caused by the slowest board, we build a mathematical model to decompose workload among FPGAs. The dividing of workload is based on the logic resource, memory access bandwidth, and communication bandwidth of each FPGA chip. Our accelerator can achieve two orders of magnitude speedup compared with CPU implementation.http://dx.doi.org/10.1155/2018/6784319 |
| spellingShingle | Shuaizhi Guo Tianqi Wang Linfeng Tao Teng Tian Zikun Xiang Xi Jin RP-Ring: A Heterogeneous Multi-FPGA Accelerator International Journal of Reconfigurable Computing |
| title | RP-Ring: A Heterogeneous Multi-FPGA Accelerator |
| title_full | RP-Ring: A Heterogeneous Multi-FPGA Accelerator |
| title_fullStr | RP-Ring: A Heterogeneous Multi-FPGA Accelerator |
| title_full_unstemmed | RP-Ring: A Heterogeneous Multi-FPGA Accelerator |
| title_short | RP-Ring: A Heterogeneous Multi-FPGA Accelerator |
| title_sort | rp ring a heterogeneous multi fpga accelerator |
| url | http://dx.doi.org/10.1155/2018/6784319 |
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