An Area-Efficient TMR Architecture Inspired From Fast FIR Algorithm for Fault Tolerance
High-end commercial silicon chips used in aerospace and other industries utilize technology nodes at deep sub-micron levels. Efforts are underway to assess the feasibility of integrating even smaller nano-scale devices for secure communication, high-speed computing, and data storage. Due to radiatio...
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| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
IEEE
2024-01-01
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| Series: | IEEE Access |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/10767249/ |
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