Investigation of SiC MOSFET Structures for Surge Robustness in the Third Quadrant Under Various <inline-formula><tex-math notation="LaTeX">$V_{\text{GS}}$</tex-math></inline-formula> Biases
In this work, SiC planar-gate MOSFET (PG-MOS), SiC short-channel (0.3<inline-formula><tex-math notation="LaTeX">$\mathbf {\mu m}$</tex-math></inline-formula>) MOSFET (SCMOS), and SiC JBSFET are tested for the third quadrant I-V temperature characteristics and surge...
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| Main Authors: | , , , , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
IEEE
2025-01-01
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| Series: | IEEE Open Journal of Power Electronics |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/11023073/ |
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| Summary: | In this work, SiC planar-gate MOSFET (PG-MOS), SiC short-channel (0.3<inline-formula><tex-math notation="LaTeX">$\mathbf {\mu m}$</tex-math></inline-formula>) MOSFET (SCMOS), and SiC JBSFET are tested for the third quadrant I-V temperature characteristics and surge current capability at different gate-source bias voltage. The I-V temperature curves and the TCAD simulation reveal that different device structures exhibit distinct temperature variation trends due to different current conduction paths. The surge test results indicate that SiC PGMOS and SiC SCMOS exhibit bipolar conduction modes at <inline-formula><tex-math notation="LaTeX">${\mathit{V}}_{\mathbf{GS}} = 0$</tex-math></inline-formula> V and <inline-formula><tex-math notation="LaTeX">${\mathit{V}}_{\mathbf{GS}} = -10$</tex-math></inline-formula> V. SiC JBSFET operates in a unipolar conduction mode prior to the surge current density threshold of 998.3 <inline-formula><tex-math notation="LaTeX">$\mathbf {A}/\mathbf {cm}^{\mathbf {2}}$</tex-math></inline-formula>, after which it transitions to a post-bipolar conduction mode, similar to SiC JBS diode. Finally, the failure mechanism is analyzed. The surge current crowding in the edge termination region is a key factor affecting the surge capability of SiC PGMOS. Reducing channel length leads to premature breakdown of the gate-source dielectric layer in SiC SCMOS at <inline-formula><tex-math notation="LaTeX">${\mathit{V}}_{\mathbf{GS}} = 0$</tex-math></inline-formula> V but enhances the surge ability at <inline-formula><tex-math notation="LaTeX">${\mathit{V}}_{\mathbf{GS}} = -10$</tex-math></inline-formula> V. The thermal stress induced by the surge current in SiC JBSFET causes large-scale damage to the source metal and cells, resulting in a short circuit between the gate, source, and drain. |
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| ISSN: | 2644-1314 |