An improved TDM-based controller for a multilevel three-phase active frontend with variable DC ratios: The extended Negev rectifier
This paper presents an improved Time-Division-Multiplexing (TDM) based controller for a recently introduced multilevel three-phase (3ɸ) active frontend called the Negev rectifier. The new controller expands the Negev rectifier to attain a DC-link supply of either Equal DC Sources (EDCS) or Unequal D...
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| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
Elsevier
2025-04-01
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| Series: | Alexandria Engineering Journal |
| Subjects: | |
| Online Access: | http://www.sciencedirect.com/science/article/pii/S1110016825001553 |
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| Summary: | This paper presents an improved Time-Division-Multiplexing (TDM) based controller for a recently introduced multilevel three-phase (3ɸ) active frontend called the Negev rectifier. The new controller expands the Negev rectifier to attain a DC-link supply of either Equal DC Sources (EDCS) or Unequal DC Sources (UDCS) with variable DC ratios up to 1:5 while preserving the power factor correction functionality of the original Negev rectifier and reducing its switching frequency by more than 50 %. When validated as a frontend solution for UDCS-based MultiPoint Clamped (MPC) 3ɸ Multilevel Inverters (MLI), both staircase modulation and pulse-width modulation schemes are supported, achieving 16.3 % reduction in Line-voltage THD (LTHD) compared to conventional approaches. This allows UDCS-based voltage and current THD minimization, traditionally limited to cascaded H-bridge MLIs, to be adapted into AC-source-fed MLIs of the MPC topologies, better suited for 3ɸ applications. The Extended Negev Multilevel Rectifier (MLR) supports 3–8 output voltage levels (N). It eliminates MLI-side voltage balancing, making it suitable for various applications from low-voltage (400 V) aircraft systems to medium-voltage marine electrical distribution or any grid-fed MLR-MLI back-to-back power conversion system demanding high power quality. The controller was verified through comprehensive testing, including digital simulations, Processor-In-Loop (PIL) emulation, and Controller-Hardware-In-Loop (C-HIL) experiments across 4-, 5-, and 7-level configurations. Experimental results have revealed a current THD as low as 2.36 % with a voltage ripple of 1.2 % in a 4-level UDCS MLR configuration. |
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| ISSN: | 1110-0168 |