Development of a SoC for Digital Television Set-Top Box: Architecture and System Integration Issues
This work presents the integration of several IPs to generate a system-on-chip (SoC) for digital television set-top box compliant to the SBTVD standard. Embedded consumer electronics for multimedia applications like video processing systems require large storage capacity and high bandwidth memory. A...
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| Format: | Article |
| Language: | English |
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Wiley
2013-01-01
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| Series: | International Journal of Reconfigurable Computing |
| Online Access: | http://dx.doi.org/10.1155/2013/783501 |
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| _version_ | 1849387270117785600 |
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| author | André Borin Soares Alexsandro Cristóvão Bonatto Altamiro Amadeu Susin |
| author_facet | André Borin Soares Alexsandro Cristóvão Bonatto Altamiro Amadeu Susin |
| author_sort | André Borin Soares |
| collection | DOAJ |
| description | This work presents the integration of several IPs to generate a system-on-chip (SoC) for digital television set-top box compliant to the SBTVD standard. Embedded consumer electronics for multimedia applications like video processing systems require large storage capacity and high bandwidth memory. Also, those systems are built from heterogeneous processing units, designed to perform specific tasks in order to maximize the overall system efficiency. A single off-chip memory is generally shared between the processing units to reduce power and save costs. The external memory access is one bottleneck when decoding high-definition video sequences in real time. In this work, a four-level memory hierarchy was designed to manage the decoded video in macroblock granularity with low latency. The use of the memory hierarchy in the system design is challenging because it impacts the system integration process and IP reuse in a collaborative design team. Practical strategies used to solve integration problems are discussed in this text. The SoC architecture was validated and is being progressively prototyped using a Xilinx Virtex-5 FPGA board. |
| format | Article |
| id | doaj-art-2f3df027d2bf46bf902e8b3149d7f349 |
| institution | Kabale University |
| issn | 1687-7195 1687-7209 |
| language | English |
| publishDate | 2013-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | International Journal of Reconfigurable Computing |
| spelling | doaj-art-2f3df027d2bf46bf902e8b3149d7f3492025-08-20T03:55:16ZengWileyInternational Journal of Reconfigurable Computing1687-71951687-72092013-01-01201310.1155/2013/783501783501Development of a SoC for Digital Television Set-Top Box: Architecture and System Integration IssuesAndré Borin Soares0Alexsandro Cristóvão Bonatto1Altamiro Amadeu Susin2PGMICRO, UFRGS, Avenida Bento Gonçalves 9500, 91501-970 Porto Alegre, RS, BrazilPGMICRO, UFRGS, Avenida Bento Gonçalves 9500, 91501-970 Porto Alegre, RS, BrazilPGMICRO, UFRGS, Avenida Bento Gonçalves 9500, 91501-970 Porto Alegre, RS, BrazilThis work presents the integration of several IPs to generate a system-on-chip (SoC) for digital television set-top box compliant to the SBTVD standard. Embedded consumer electronics for multimedia applications like video processing systems require large storage capacity and high bandwidth memory. Also, those systems are built from heterogeneous processing units, designed to perform specific tasks in order to maximize the overall system efficiency. A single off-chip memory is generally shared between the processing units to reduce power and save costs. The external memory access is one bottleneck when decoding high-definition video sequences in real time. In this work, a four-level memory hierarchy was designed to manage the decoded video in macroblock granularity with low latency. The use of the memory hierarchy in the system design is challenging because it impacts the system integration process and IP reuse in a collaborative design team. Practical strategies used to solve integration problems are discussed in this text. The SoC architecture was validated and is being progressively prototyped using a Xilinx Virtex-5 FPGA board.http://dx.doi.org/10.1155/2013/783501 |
| spellingShingle | André Borin Soares Alexsandro Cristóvão Bonatto Altamiro Amadeu Susin Development of a SoC for Digital Television Set-Top Box: Architecture and System Integration Issues International Journal of Reconfigurable Computing |
| title | Development of a SoC for Digital Television Set-Top Box: Architecture and System Integration Issues |
| title_full | Development of a SoC for Digital Television Set-Top Box: Architecture and System Integration Issues |
| title_fullStr | Development of a SoC for Digital Television Set-Top Box: Architecture and System Integration Issues |
| title_full_unstemmed | Development of a SoC for Digital Television Set-Top Box: Architecture and System Integration Issues |
| title_short | Development of a SoC for Digital Television Set-Top Box: Architecture and System Integration Issues |
| title_sort | development of a soc for digital television set top box architecture and system integration issues |
| url | http://dx.doi.org/10.1155/2013/783501 |
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