A novel self‐timing CMOS first‐edge take‐all circuit for on‐chip communication systems
Abstract In today's communication systems, it has become prominent for processing elements (PEs) to receive requests with simultaneous, conflicting signals, which are unpredicted and randomly triggered. In such a case, multiple overlapping signal requests can potentially compete in the same PE...
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| Format: | Article |
| Language: | English |
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Wiley
2023-07-01
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| Series: | IET Computers & Digital Techniques |
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| Online Access: | https://doi.org/10.1049/cdt2.12059 |
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| author | Saleh Abdelhafeez Shadi M. S. Harb |
| author_facet | Saleh Abdelhafeez Shadi M. S. Harb |
| author_sort | Saleh Abdelhafeez |
| collection | DOAJ |
| description | Abstract In today's communication systems, it has become prominent for processing elements (PEs) to receive requests with simultaneous, conflicting signals, which are unpredicted and randomly triggered. In such a case, multiple overlapping signal requests can potentially compete in the same PE causing erroneous operations or a halt of the communication cycle. The authors propose a self‐timing CMOS first‐edge take‐all (FETA) circuit architecture, which examines two overlapping signals’ requests, and outputs only the leading‐edge signal while the lagging‐edge signal's request is declined. The FETA circuit functionality is considered as an essential component in First‐In‐First‐Out for metastability avoidance, which usually occurs between the write and read overlapping requests for applications related to Internet of Things, Network‐on‐Chips, and microprocessor memory management units. HSPICE simulations for a 90 nm CMOS technology are used to verify the speed up to 1 GHz. Besides, the achievable resolution is in the order of 20 ps considering process variation sensitivity based on design inheriting symmetric timing paths between the two signals. Additionally, the proposed circuit architecture adopts a self‐timing scheme obviating the overhead synchronisation circuitry, which comprises 12 D‐Type Flip‐Flops with about 300 transistors. This design is suited for HDL synthesis and FPGA application features. |
| format | Article |
| id | doaj-art-2f346327d2cb4f44ab55f1b9f174dcbd |
| institution | OA Journals |
| issn | 1751-8601 1751-861X |
| language | English |
| publishDate | 2023-07-01 |
| publisher | Wiley |
| record_format | Article |
| series | IET Computers & Digital Techniques |
| spelling | doaj-art-2f346327d2cb4f44ab55f1b9f174dcbd2025-08-20T02:08:12ZengWileyIET Computers & Digital Techniques1751-86011751-861X2023-07-01173-414114810.1049/cdt2.12059A novel self‐timing CMOS first‐edge take‐all circuit for on‐chip communication systemsSaleh Abdelhafeez0Shadi M. S. Harb1Department of Computer Engineering Jordan University of Science and Technology Irbid JordanElectrical and Computer Engineering Department University of Florida Gainesville Florida USAAbstract In today's communication systems, it has become prominent for processing elements (PEs) to receive requests with simultaneous, conflicting signals, which are unpredicted and randomly triggered. In such a case, multiple overlapping signal requests can potentially compete in the same PE causing erroneous operations or a halt of the communication cycle. The authors propose a self‐timing CMOS first‐edge take‐all (FETA) circuit architecture, which examines two overlapping signals’ requests, and outputs only the leading‐edge signal while the lagging‐edge signal's request is declined. The FETA circuit functionality is considered as an essential component in First‐In‐First‐Out for metastability avoidance, which usually occurs between the write and read overlapping requests for applications related to Internet of Things, Network‐on‐Chips, and microprocessor memory management units. HSPICE simulations for a 90 nm CMOS technology are used to verify the speed up to 1 GHz. Besides, the achievable resolution is in the order of 20 ps considering process variation sensitivity based on design inheriting symmetric timing paths between the two signals. Additionally, the proposed circuit architecture adopts a self‐timing scheme obviating the overhead synchronisation circuitry, which comprises 12 D‐Type Flip‐Flops with about 300 transistors. This design is suited for HDL synthesis and FPGA application features.https://doi.org/10.1049/cdt2.12059CMOS integrated circuitsnetwork‐on‐chipVLSI |
| spellingShingle | Saleh Abdelhafeez Shadi M. S. Harb A novel self‐timing CMOS first‐edge take‐all circuit for on‐chip communication systems IET Computers & Digital Techniques CMOS integrated circuits network‐on‐chip VLSI |
| title | A novel self‐timing CMOS first‐edge take‐all circuit for on‐chip communication systems |
| title_full | A novel self‐timing CMOS first‐edge take‐all circuit for on‐chip communication systems |
| title_fullStr | A novel self‐timing CMOS first‐edge take‐all circuit for on‐chip communication systems |
| title_full_unstemmed | A novel self‐timing CMOS first‐edge take‐all circuit for on‐chip communication systems |
| title_short | A novel self‐timing CMOS first‐edge take‐all circuit for on‐chip communication systems |
| title_sort | novel self timing cmos first edge take all circuit for on chip communication systems |
| topic | CMOS integrated circuits network‐on‐chip VLSI |
| url | https://doi.org/10.1049/cdt2.12059 |
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