A Low Noise Amplifier with Low Voltage, Low Power Consumption, and Improved Linearity at 5 GHz
In this paper a low-noise amplifier with 0.6 V supply voltage, low power consumption, and improved linearity at= 5 GHz is introduced in 0.18 µm CMOS technology. By using a feed-forward structure and a multi-gated configuration in the proposed circuit, linearity of the circuit is significantly improv...
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| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
| Published: |
OICC Press
2024-02-01
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| Series: | Majlesi Journal of Electrical Engineering |
| Subjects: | |
| Online Access: | https://oiccpress.com/mjee/article/view/4776 |
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| Summary: | In this paper a low-noise amplifier with 0.6 V supply voltage, low power consumption, and improved linearity at= 5 GHz is introduced in 0.18 µm CMOS technology. By using a feed-forward structure and a multi-gated configuration in the proposed circuit, linearity of the circuit is significantly improved, while only 122 µW more power is consumed compared to conventional folded cascode structure, and the other circuit parameters are similar. In addition, the Volterra series is used for nonlinear analysis and to evaluate the linearity improvement of the proposed circuit. There is also a noteworthy superiority over compared published works in the figure of merit. The suggested low-noise amplifier (LNA) at 1.28 mW DC power consumption provides 9.6 dB gain and a noise figure of 3.24 dB. It is achieved whilst the third order interception point has been improved by 10 dB and equals 0.0 dBm. In the operating frequency the circuit displays satisfactory input and output impedance matching. Finally, throughout the whole circuit bandwidth input and output isolation is below â27 dB. |
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| ISSN: | 2345-377X 2345-3796 |