Multiloop Parallelisation Using Unrolling and Fission
A technique for parallelising multiple loops in a heterogeneous computing system is presented. Loops are first unrolled and then broken up into multiple tasks which are mapped to reconfigurable hardware. A performance-driven optimisation is applied to find the best unrolling factor for each loop und...
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| Main Authors: | , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
Wiley
2010-01-01
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| Series: | International Journal of Reconfigurable Computing |
| Online Access: | http://dx.doi.org/10.1155/2010/475620 |
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| _version_ | 1832564526004830208 |
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| author | Yuet Ming Lam José Gabriel F. Coutinho Chun Hok Ho Philip Heng Wai Leong Wayne Luk |
| author_facet | Yuet Ming Lam José Gabriel F. Coutinho Chun Hok Ho Philip Heng Wai Leong Wayne Luk |
| author_sort | Yuet Ming Lam |
| collection | DOAJ |
| description | A technique for parallelising multiple loops in a heterogeneous computing system is presented. Loops are first unrolled and then broken up into multiple tasks which are mapped to reconfigurable hardware. A performance-driven optimisation is applied to find the best unrolling factor for each loop under hardware size constraints. The approach is demonstrated using three applications: speech recognition, image processing, and the N-Body problem. Experimental results show that a maximum speedup of 34 is achieved on a 274 MHz FPGA for the N-Body over a 2.6 GHz microprocessor, which is 4.1 times higher than that of an approach without unrolling. |
| format | Article |
| id | doaj-art-2c546ca0ecaa4a76ac8ca8252b88ed47 |
| institution | Kabale University |
| issn | 1687-7195 1687-7209 |
| language | English |
| publishDate | 2010-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | International Journal of Reconfigurable Computing |
| spelling | doaj-art-2c546ca0ecaa4a76ac8ca8252b88ed472025-02-03T01:10:48ZengWileyInternational Journal of Reconfigurable Computing1687-71951687-72092010-01-01201010.1155/2010/475620475620Multiloop Parallelisation Using Unrolling and FissionYuet Ming Lam0José Gabriel F. Coutinho1Chun Hok Ho2Philip Heng Wai Leong3Wayne Luk4Faculty of Information Technology, Macau University of Science and Technology, Taipa, Macau, ChinaDepartment of Computing, Imperial College London, London, UKDepartment of Computing, Imperial College London, London, UKSchool of Electrical and Information Engineering, University of Sydney, Sydney, NSW, AustraliaDepartment of Computing, Imperial College London, London, UKA technique for parallelising multiple loops in a heterogeneous computing system is presented. Loops are first unrolled and then broken up into multiple tasks which are mapped to reconfigurable hardware. A performance-driven optimisation is applied to find the best unrolling factor for each loop under hardware size constraints. The approach is demonstrated using three applications: speech recognition, image processing, and the N-Body problem. Experimental results show that a maximum speedup of 34 is achieved on a 274 MHz FPGA for the N-Body over a 2.6 GHz microprocessor, which is 4.1 times higher than that of an approach without unrolling.http://dx.doi.org/10.1155/2010/475620 |
| spellingShingle | Yuet Ming Lam José Gabriel F. Coutinho Chun Hok Ho Philip Heng Wai Leong Wayne Luk Multiloop Parallelisation Using Unrolling and Fission International Journal of Reconfigurable Computing |
| title | Multiloop Parallelisation Using Unrolling and Fission |
| title_full | Multiloop Parallelisation Using Unrolling and Fission |
| title_fullStr | Multiloop Parallelisation Using Unrolling and Fission |
| title_full_unstemmed | Multiloop Parallelisation Using Unrolling and Fission |
| title_short | Multiloop Parallelisation Using Unrolling and Fission |
| title_sort | multiloop parallelisation using unrolling and fission |
| url | http://dx.doi.org/10.1155/2010/475620 |
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