A VLSI Implementation of Rank-Order Searching Circuit Employing a Time-Domain Technique

We present a compact and low-power rank-order searching (ROS) circuit that can be used for building associative memories and rank-order filters (ROFs) by employing time-domain computation and floating-gate MOS techniques. The architecture inherits the accuracy and programmability of digital implemen...

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Main Authors: Trong-Tu Bui, Tadashi Shibata
Format: Article
Language:English
Published: Wiley 2013-01-01
Series:Journal of Engineering
Online Access:http://dx.doi.org/10.1155/2013/759761
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author Trong-Tu Bui
Tadashi Shibata
author_facet Trong-Tu Bui
Tadashi Shibata
author_sort Trong-Tu Bui
collection DOAJ
description We present a compact and low-power rank-order searching (ROS) circuit that can be used for building associative memories and rank-order filters (ROFs) by employing time-domain computation and floating-gate MOS techniques. The architecture inherits the accuracy and programmability of digital implementations as well as the compactness and low-power consumption of analog ones. We aim to implement identification function as the first priority objective. Filtering function would be implemented once the location identification function has been carried out. The prototype circuit was designed and fabricated in a 0.18 μm CMOS technology. It consumes only 132.3 μW for an eight-input demonstration case.
format Article
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institution Kabale University
issn 2314-4904
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language English
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publisher Wiley
record_format Article
series Journal of Engineering
spelling doaj-art-2b6cfdfb577a48f2adb7a1786a40fbd52025-02-03T01:26:22ZengWileyJournal of Engineering2314-49042314-49122013-01-01201310.1155/2013/759761759761A VLSI Implementation of Rank-Order Searching Circuit Employing a Time-Domain TechniqueTrong-Tu Bui0Tadashi Shibata1Faculty of Electronics and Telecommunications, University of Science, VNU-HCM, Ho Chi Minh City, VietnamDepartment of Electrical Engineering and Information Systems, The University of Tokyo, Tokyo 113-8656, JapanWe present a compact and low-power rank-order searching (ROS) circuit that can be used for building associative memories and rank-order filters (ROFs) by employing time-domain computation and floating-gate MOS techniques. The architecture inherits the accuracy and programmability of digital implementations as well as the compactness and low-power consumption of analog ones. We aim to implement identification function as the first priority objective. Filtering function would be implemented once the location identification function has been carried out. The prototype circuit was designed and fabricated in a 0.18 μm CMOS technology. It consumes only 132.3 μW for an eight-input demonstration case.http://dx.doi.org/10.1155/2013/759761
spellingShingle Trong-Tu Bui
Tadashi Shibata
A VLSI Implementation of Rank-Order Searching Circuit Employing a Time-Domain Technique
Journal of Engineering
title A VLSI Implementation of Rank-Order Searching Circuit Employing a Time-Domain Technique
title_full A VLSI Implementation of Rank-Order Searching Circuit Employing a Time-Domain Technique
title_fullStr A VLSI Implementation of Rank-Order Searching Circuit Employing a Time-Domain Technique
title_full_unstemmed A VLSI Implementation of Rank-Order Searching Circuit Employing a Time-Domain Technique
title_short A VLSI Implementation of Rank-Order Searching Circuit Employing a Time-Domain Technique
title_sort vlsi implementation of rank order searching circuit employing a time domain technique
url http://dx.doi.org/10.1155/2013/759761
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