Frequency-Decoupled Dual-Stage Inverse Lithography Optimization via Hierarchical Sampling and Morphological Enhancement
Inverse lithography technology (ILT) plays a pivotal role in advanced semiconductor manufacturing because it enables pixel-level mask modifications, significantly enhances pattern fidelity, and expands process windows. However, traditional gradient-based ILT methods often struggle with the trade-off...
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| Main Authors: | , , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
MDPI AG
2025-04-01
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| Series: | Micromachines |
| Subjects: | |
| Online Access: | https://www.mdpi.com/2072-666X/16/5/515 |
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| Summary: | Inverse lithography technology (ILT) plays a pivotal role in advanced semiconductor manufacturing because it enables pixel-level mask modifications, significantly enhances pattern fidelity, and expands process windows. However, traditional gradient-based ILT methods often struggle with the trade-off between imaging fidelity and mask manufacturability due to coupled optimization objectives. We propose a frequency-separated dual-stage optimization framework (FD-ILT) that strategically decouples these conflicting objectives by exploiting the inherent low-pass characteristics of lithographic systems. The first stage optimizes low-frequency (LF) components using hierarchical downsampling to generate a high-fidelity continuous transmission mask. This approach reduces computational complexity while refining resolution progressively. The second stage enforces manufacturability by exclusively adjusting high-frequency (HF) features through morphological regularization and progressive binarization penalties while maintaining the mask LF to preserve imaging accuracy. Our method achieves simultaneous control of both aspects by eliminating gradient conflicts between fidelity and manufacturing constraints. The simulation results demonstrate that FD-ILT achieves superior imaging quality and manufacturability compared to conventional gradient-based ILT methods, offering a scalable solution for advanced semiconductor nodes. |
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| ISSN: | 2072-666X |