Implementation of Boolean Logic Functions Through Double Gate FD-SOI MOSFET
This work showcases the implementation of 16 Boolean logic functions through a double-gate (DG) fully depleted (FD) Silicon-on-Insulator (SOI) Metal-Oxide-Semiconductor-Field-Effect-Transistor (MOSFET). The DG-FD-SOI device with an independent gate operation highlights that Boolean logic functions c...
Saved in:
| Main Authors: | , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
IEEE
2024-01-01
|
| Series: | IEEE Access |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/10669549/ |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| _version_ | 1850265048040079360 |
|---|---|
| author | Md. Hasan Raza Ansari Nazek El-Atab |
| author_facet | Md. Hasan Raza Ansari Nazek El-Atab |
| author_sort | Md. Hasan Raza Ansari |
| collection | DOAJ |
| description | This work showcases the implementation of 16 Boolean logic functions through a double-gate (DG) fully depleted (FD) Silicon-on-Insulator (SOI) Metal-Oxide-Semiconductor-Field-Effect-Transistor (MOSFET). The DG-FD-SOI device with an independent gate operation highlights that Boolean logic functions can be implemented in two steps (Program and Read), and Boolean logic output “High” (“1”) and “Low” (“0”) depends on the floating body effect. The Program (Step 1) operation is based on band-to-band tunneling and forward bias mechanisms, while the Read (Step 2) operation is based on drift and impact ionization mechanism. The program and read operations for logic-in-memory computing are performed in ~10 ns and consume low energy (<inline-formula> <tex-math notation="LaTeX">$\sim 4.04\times 10 ^{-14}$ </tex-math></inline-formula> J) during the read operation. The results also show that the device with optimized device dimensions, biasing, and timing scheme achieves a drain current ratio of <inline-formula> <tex-math notation="LaTeX">$\sim 10^{5}$ </tex-math></inline-formula>. These results reveal that DG-FD-SOI-based MOSFET for logic-in-memory computing is a compelling alternative to the limitations of von Neumann architectures, offering significant speed and energy efficiency advantages. |
| format | Article |
| id | doaj-art-29b752bdb2a743bb82877015fa1952de |
| institution | OA Journals |
| issn | 2169-3536 |
| language | English |
| publishDate | 2024-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj-art-29b752bdb2a743bb82877015fa1952de2025-08-20T01:54:33ZengIEEEIEEE Access2169-35362024-01-011212881012881510.1109/ACCESS.2024.345647710669549Implementation of Boolean Logic Functions Through Double Gate FD-SOI MOSFETMd. Hasan Raza Ansari0https://orcid.org/0000-0002-8587-4588Nazek El-Atab1https://orcid.org/0000-0002-2296-2003SAMA Labs, Division of Computer, Electrical and Mathematical Science and Engineering (CEMSE) Division, Electrical and Computer Engineering, King Abdullah University of Science and Technology (KAUST), Thuwal, Saudi ArabiaSAMA Labs, Division of Computer, Electrical and Mathematical Science and Engineering (CEMSE) Division, Electrical and Computer Engineering, King Abdullah University of Science and Technology (KAUST), Thuwal, Saudi ArabiaThis work showcases the implementation of 16 Boolean logic functions through a double-gate (DG) fully depleted (FD) Silicon-on-Insulator (SOI) Metal-Oxide-Semiconductor-Field-Effect-Transistor (MOSFET). The DG-FD-SOI device with an independent gate operation highlights that Boolean logic functions can be implemented in two steps (Program and Read), and Boolean logic output “High” (“1”) and “Low” (“0”) depends on the floating body effect. The Program (Step 1) operation is based on band-to-band tunneling and forward bias mechanisms, while the Read (Step 2) operation is based on drift and impact ionization mechanism. The program and read operations for logic-in-memory computing are performed in ~10 ns and consume low energy (<inline-formula> <tex-math notation="LaTeX">$\sim 4.04\times 10 ^{-14}$ </tex-math></inline-formula> J) during the read operation. The results also show that the device with optimized device dimensions, biasing, and timing scheme achieves a drain current ratio of <inline-formula> <tex-math notation="LaTeX">$\sim 10^{5}$ </tex-math></inline-formula>. These results reveal that DG-FD-SOI-based MOSFET for logic-in-memory computing is a compelling alternative to the limitations of von Neumann architectures, offering significant speed and energy efficiency advantages.https://ieeexplore.ieee.org/document/10669549/Double gateSOIcapacitorless DRAMin-memorylogic gatesAND |
| spellingShingle | Md. Hasan Raza Ansari Nazek El-Atab Implementation of Boolean Logic Functions Through Double Gate FD-SOI MOSFET IEEE Access Double gate SOI capacitorless DRAM in-memory logic gates AND |
| title | Implementation of Boolean Logic Functions Through Double Gate FD-SOI MOSFET |
| title_full | Implementation of Boolean Logic Functions Through Double Gate FD-SOI MOSFET |
| title_fullStr | Implementation of Boolean Logic Functions Through Double Gate FD-SOI MOSFET |
| title_full_unstemmed | Implementation of Boolean Logic Functions Through Double Gate FD-SOI MOSFET |
| title_short | Implementation of Boolean Logic Functions Through Double Gate FD-SOI MOSFET |
| title_sort | implementation of boolean logic functions through double gate fd soi mosfet |
| topic | Double gate SOI capacitorless DRAM in-memory logic gates AND |
| url | https://ieeexplore.ieee.org/document/10669549/ |
| work_keys_str_mv | AT mdhasanrazaansari implementationofbooleanlogicfunctionsthroughdoublegatefdsoimosfet AT nazekelatab implementationofbooleanlogicfunctionsthroughdoublegatefdsoimosfet |