A fully differential switched‐capacitor integrator based programmable resolution hybrid ADC architecture for biomedical applications
Abstract A novel switched‐capacitor integrator based programmable resolution analog to digital converter (ADC) architecture is proposed. The proposed hybrid ADC architecture can be switched between successive approximation register (SAR) and delta‐sigma modulator (DSM) mode in 8‐bit to 15‐bit resolu...
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| Format: | Article |
| Language: | English |
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Wiley
2021-03-01
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| Series: | IET Circuits, Devices and Systems |
| Online Access: | https://doi.org/10.1049/cds2.12014 |
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| author | Sreenivasulu Polineni Rekha S. M. S. Bhat |
| author_facet | Sreenivasulu Polineni Rekha S. M. S. Bhat |
| author_sort | Sreenivasulu Polineni |
| collection | DOAJ |
| description | Abstract A novel switched‐capacitor integrator based programmable resolution analog to digital converter (ADC) architecture is proposed. The proposed hybrid ADC architecture can be switched between successive approximation register (SAR) and delta‐sigma modulator (DSM) mode in 8‐bit to 15‐bit resolution. A mathematical relationship showing the effect of mismatch of capacitors on ADC linearity is derived. A fully differential folded cascode operational transconductance amplifier (OTA) operating in a weak inversion region is designed using gm/ID technique with programmable unity gain bandwidth and slew rate. The designed OTA offers 83 dB DC gain. The proposed ADC, designed and laid out in UMC 180 nm standard CMOS technology, occupies an area of 0.228 mm2. The ADC resolution is programmable from 8‐bit to 15‐bit using a 3‐bit control bus (res[2 : 0]). The hybrid ADC operates in SAR mode from 8‐bit to 11‐bit resolutions and as the first‐order DSM with a multi‐bit quantizer in 12‐bit to 15‐bit resolutions. The dynamic performance of the proposed ADC is verified through post‐layout simulations with a supply voltage of 1.8 V. It exhibits a signal‐to‐noise and distortion ratio of 45–86 dB and consumes a power of 0.86–98 μW across target resolutions (8–15 bits). |
| format | Article |
| id | doaj-art-278e25155def40bc91a3d9f2901ed3c4 |
| institution | Kabale University |
| issn | 1751-858X 1751-8598 |
| language | English |
| publishDate | 2021-03-01 |
| publisher | Wiley |
| record_format | Article |
| series | IET Circuits, Devices and Systems |
| spelling | doaj-art-278e25155def40bc91a3d9f2901ed3c42025-02-03T01:29:39ZengWileyIET Circuits, Devices and Systems1751-858X1751-85982021-03-0115214115510.1049/cds2.12014A fully differential switched‐capacitor integrator based programmable resolution hybrid ADC architecture for biomedical applicationsSreenivasulu Polineni0Rekha S.1M. S. Bhat2Department of ECE National Institute of Technology Karnataka Surathkal Karnataka IndiaDepartment of ECE National Institute of Technology Karnataka Surathkal Karnataka IndiaDepartment of ECE National Institute of Technology Karnataka Surathkal Karnataka IndiaAbstract A novel switched‐capacitor integrator based programmable resolution analog to digital converter (ADC) architecture is proposed. The proposed hybrid ADC architecture can be switched between successive approximation register (SAR) and delta‐sigma modulator (DSM) mode in 8‐bit to 15‐bit resolution. A mathematical relationship showing the effect of mismatch of capacitors on ADC linearity is derived. A fully differential folded cascode operational transconductance amplifier (OTA) operating in a weak inversion region is designed using gm/ID technique with programmable unity gain bandwidth and slew rate. The designed OTA offers 83 dB DC gain. The proposed ADC, designed and laid out in UMC 180 nm standard CMOS technology, occupies an area of 0.228 mm2. The ADC resolution is programmable from 8‐bit to 15‐bit using a 3‐bit control bus (res[2 : 0]). The hybrid ADC operates in SAR mode from 8‐bit to 11‐bit resolutions and as the first‐order DSM with a multi‐bit quantizer in 12‐bit to 15‐bit resolutions. The dynamic performance of the proposed ADC is verified through post‐layout simulations with a supply voltage of 1.8 V. It exhibits a signal‐to‐noise and distortion ratio of 45–86 dB and consumes a power of 0.86–98 μW across target resolutions (8–15 bits).https://doi.org/10.1049/cds2.12014 |
| spellingShingle | Sreenivasulu Polineni Rekha S. M. S. Bhat A fully differential switched‐capacitor integrator based programmable resolution hybrid ADC architecture for biomedical applications IET Circuits, Devices and Systems |
| title | A fully differential switched‐capacitor integrator based programmable resolution hybrid ADC architecture for biomedical applications |
| title_full | A fully differential switched‐capacitor integrator based programmable resolution hybrid ADC architecture for biomedical applications |
| title_fullStr | A fully differential switched‐capacitor integrator based programmable resolution hybrid ADC architecture for biomedical applications |
| title_full_unstemmed | A fully differential switched‐capacitor integrator based programmable resolution hybrid ADC architecture for biomedical applications |
| title_short | A fully differential switched‐capacitor integrator based programmable resolution hybrid ADC architecture for biomedical applications |
| title_sort | fully differential switched capacitor integrator based programmable resolution hybrid adc architecture for biomedical applications |
| url | https://doi.org/10.1049/cds2.12014 |
| work_keys_str_mv | AT sreenivasulupolineni afullydifferentialswitchedcapacitorintegratorbasedprogrammableresolutionhybridadcarchitectureforbiomedicalapplications AT rekhas afullydifferentialswitchedcapacitorintegratorbasedprogrammableresolutionhybridadcarchitectureforbiomedicalapplications AT msbhat afullydifferentialswitchedcapacitorintegratorbasedprogrammableresolutionhybridadcarchitectureforbiomedicalapplications AT sreenivasulupolineni fullydifferentialswitchedcapacitorintegratorbasedprogrammableresolutionhybridadcarchitectureforbiomedicalapplications AT rekhas fullydifferentialswitchedcapacitorintegratorbasedprogrammableresolutionhybridadcarchitectureforbiomedicalapplications AT msbhat fullydifferentialswitchedcapacitorintegratorbasedprogrammableresolutionhybridadcarchitectureforbiomedicalapplications |