Pasithea-1: An Energy-Efficient Sequential Reconfigurable Array With CPU-Like Programmability
This work presents Pasithea-1, a coarse-grained reconfigurable array (CGRA) that combines energy efficiency with CPU-like programmability. Its extensible instruction set uses sequential control flow in code fragments of up to 64 RISC-like instructions, which encode control and dataflow graphs in adj...
Saved in:
| Main Authors: | Tobias Kaiser, Esther Gottschalk, Kai Biethahn, Friedel Gerfers |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
IEEE
2025-01-01
|
| Series: | IEEE Open Journal of Circuits and Systems |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/10802954/ |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Similar Items
-
A Framework for Hardware-Accelerated Services Using Partially Reconfigurable SoCs
by: MACHIDON, O. M., et al.
Published: (2016-05-01) -
Interface design of HART modulation and demodulation chip
by: Zhang Liguo, et al.
Published: (2022-04-01) -
Preamble Design and Noncoherent ToA Estimation for Pulse-Based Wireless Networks-on-Chip Communications in the Terahertz Band
by: Pankaj Singh, et al.
Published: (2025-01-01) -
Data Rates Assessment on L2–L3 CPU Bus and Bus between CPU and RAM in Modern CPUs
by: Maria S. Komar
Published: (2017-08-01) -
CFD-simulation of impact jet radiator for thermal testing of microprocessors
by: V. E. Trofimov, et al.
Published: (2018-12-01)