Pasithea-1: An Energy-Efficient Sequential Reconfigurable Array With CPU-Like Programmability
This work presents Pasithea-1, a coarse-grained reconfigurable array (CGRA) that combines energy efficiency with CPU-like programmability. Its extensible instruction set uses sequential control flow in code fragments of up to 64 RISC-like instructions, which encode control and dataflow graphs in adj...
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IEEE
2025-01-01
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| Series: | IEEE Open Journal of Circuits and Systems |
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| Online Access: | https://ieeexplore.ieee.org/document/10802954/ |
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| author | Tobias Kaiser Esther Gottschalk Kai Biethahn Friedel Gerfers |
| author_facet | Tobias Kaiser Esther Gottschalk Kai Biethahn Friedel Gerfers |
| author_sort | Tobias Kaiser |
| collection | DOAJ |
| description | This work presents Pasithea-1, a coarse-grained reconfigurable array (CGRA) that combines energy efficiency with CPU-like programmability. Its extensible instruction set uses sequential control flow in code fragments of up to 64 RISC-like instructions, which encode control and dataflow graphs in adjacency lists. Combined with dedicated, uniform processing elements, this enables fast compilation from C source code (1.4 s mean compile time). Demonstrator measurements reveal energy efficiency of up to 601 int32 MIPS/mW at 0.59V and performance of up to 148 MIPS at 0.90 V. Compared to a RISC reference system, mean energy efficiency is improved by 2.24× with 1.71× higher execution times across 12 of 14 benchmarks. Program-dependent factors underlying variations in energy efficiency are identified using dynamic program analysis. To reduce operand transfer energy, seven interconnect topologies are evaluated: a flat bus, five crossbar variants and a logarithmic network. Best results are obtained for a crossbar topology, reducing mean dynamic tile energy by 19 %. Furthermore, floating-point (FP) support is added to the instruction set and evaluated using three binary-compatible microarchitectures, presenting distinct area-performance-energy tradeoffs. The interconnect and FP microarchitecture explorations demonstrate that, unlike CGRAs utilizing low-level bitstreams, Pasithea’s instruction set hides microarchitectural details, which makes it possible to optimize hardware without severing binary compatibility. |
| format | Article |
| id | doaj-art-265e6934780f427b84c3a748083893de |
| institution | Kabale University |
| issn | 2644-1225 |
| language | English |
| publishDate | 2025-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Open Journal of Circuits and Systems |
| spelling | doaj-art-265e6934780f427b84c3a748083893de2025-01-08T00:01:58ZengIEEEIEEE Open Journal of Circuits and Systems2644-12252025-01-01611310.1109/OJCAS.2024.351811010802954Pasithea-1: An Energy-Efficient Sequential Reconfigurable Array With CPU-Like ProgrammabilityTobias Kaiser0https://orcid.org/0000-0002-9301-4609Esther Gottschalk1https://orcid.org/0009-0003-4762-7046Kai Biethahn2https://orcid.org/0009-0004-0581-1651Friedel Gerfers3https://orcid.org/0000-0002-0520-1923Chair of Mixed Signal Circuit Design, Technische Universität Berlin, Berlin, GermanyFraunhofer Institute for Telecommunications, Heinrich-Hertz-Institut, Berlin, GermanyChair of Mixed Signal Circuit Design, Technische Universität Berlin, Berlin, GermanyChair of Mixed Signal Circuit Design, Technische Universität Berlin, Berlin, GermanyThis work presents Pasithea-1, a coarse-grained reconfigurable array (CGRA) that combines energy efficiency with CPU-like programmability. Its extensible instruction set uses sequential control flow in code fragments of up to 64 RISC-like instructions, which encode control and dataflow graphs in adjacency lists. Combined with dedicated, uniform processing elements, this enables fast compilation from C source code (1.4 s mean compile time). Demonstrator measurements reveal energy efficiency of up to 601 int32 MIPS/mW at 0.59V and performance of up to 148 MIPS at 0.90 V. Compared to a RISC reference system, mean energy efficiency is improved by 2.24× with 1.71× higher execution times across 12 of 14 benchmarks. Program-dependent factors underlying variations in energy efficiency are identified using dynamic program analysis. To reduce operand transfer energy, seven interconnect topologies are evaluated: a flat bus, five crossbar variants and a logarithmic network. Best results are obtained for a crossbar topology, reducing mean dynamic tile energy by 19 %. Furthermore, floating-point (FP) support is added to the instruction set and evaluated using three binary-compatible microarchitectures, presenting distinct area-performance-energy tradeoffs. The interconnect and FP microarchitecture explorations demonstrate that, unlike CGRAs utilizing low-level bitstreams, Pasithea’s instruction set hides microarchitectural details, which makes it possible to optimize hardware without severing binary compatibility.https://ieeexplore.ieee.org/document/10802954/Computer architecturereconfigurable architecturesmicroprocessor chipsenergy efficiencycode generationon-chip interconnection networks |
| spellingShingle | Tobias Kaiser Esther Gottschalk Kai Biethahn Friedel Gerfers Pasithea-1: An Energy-Efficient Sequential Reconfigurable Array With CPU-Like Programmability IEEE Open Journal of Circuits and Systems Computer architecture reconfigurable architectures microprocessor chips energy efficiency code generation on-chip interconnection networks |
| title | Pasithea-1: An Energy-Efficient Sequential Reconfigurable Array With CPU-Like Programmability |
| title_full | Pasithea-1: An Energy-Efficient Sequential Reconfigurable Array With CPU-Like Programmability |
| title_fullStr | Pasithea-1: An Energy-Efficient Sequential Reconfigurable Array With CPU-Like Programmability |
| title_full_unstemmed | Pasithea-1: An Energy-Efficient Sequential Reconfigurable Array With CPU-Like Programmability |
| title_short | Pasithea-1: An Energy-Efficient Sequential Reconfigurable Array With CPU-Like Programmability |
| title_sort | pasithea 1 an energy efficient sequential reconfigurable array with cpu like programmability |
| topic | Computer architecture reconfigurable architectures microprocessor chips energy efficiency code generation on-chip interconnection networks |
| url | https://ieeexplore.ieee.org/document/10802954/ |
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