SAR-Assisted Energy-Efficient Hybrid ADCs
The distinct advantages of low power consumption and hardware compactness make SAR ADCs especially appealing in scaled CMOS technologies, garnering significant attention. The residue left on the capacitor digital-to-analog converter (CDAC) after conversion in the SAR ADC negates the need for complex...
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| Format: | Article |
| Language: | English |
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IEEE
2024-01-01
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| Series: | IEEE Open Journal of the Solid-State Circuits Society |
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| Online Access: | https://ieeexplore.ieee.org/document/10702510/ |
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| author | Kent Edrian Lozada Dong-Jin Chang Dong-Ryeol Oh Min-Jae Seo Seung-Tak Ryu |
| author_facet | Kent Edrian Lozada Dong-Jin Chang Dong-Ryeol Oh Min-Jae Seo Seung-Tak Ryu |
| author_sort | Kent Edrian Lozada |
| collection | DOAJ |
| description | The distinct advantages of low power consumption and hardware compactness make SAR ADCs especially appealing in scaled CMOS technologies, garnering significant attention. The residue left on the capacitor digital-to-analog converter (CDAC) after conversion in the SAR ADC negates the need for complex residue extraction circuits. This crucial feature has inspired numerous SAR-assisted architectural variations, employed in a range of applications from high resolution to high speed. This article introduces several energy-efficient hybrid ADC architectures that incorporate SAR ADCs as their sub blocks, including the following: SAR-assisted subranging SAR, which saves DAC switching power and can detect skew errors for time-interleaved ADCs; SAR-flash hybrid for energy-efficient high-speed conversion; SAR-assisted dual-residue pipelined ADC, which eliminates the stringent requirement for residue gain accuracy; and SAR-assisted delta–sigma modulator (DSM) with digital-domain noise coupling, which reduces the number of required analog integrators. |
| format | Article |
| id | doaj-art-260cf35c7d72496bae624ae6ed868b05 |
| institution | Kabale University |
| issn | 2644-1349 |
| language | English |
| publishDate | 2024-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Open Journal of the Solid-State Circuits Society |
| spelling | doaj-art-260cf35c7d72496bae624ae6ed868b052025-01-25T00:03:18ZengIEEEIEEE Open Journal of the Solid-State Circuits Society2644-13492024-01-01416317510.1109/OJSSCS.2024.347200010702510SAR-Assisted Energy-Efficient Hybrid ADCsKent Edrian Lozada0https://orcid.org/0000-0002-5858-0453Dong-Jin Chang1Dong-Ryeol Oh2https://orcid.org/0000-0002-5454-5191Min-Jae Seo3https://orcid.org/0009-0006-7908-2994Seung-Tak Ryu4https://orcid.org/0000-0002-6947-7785School of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon, South KoreaDepartment of Electronics Engineering, Chungnam National University, Daejeon, South KoreaDepartment of Electronic Engineering, Jeju National University, Jeju, South KoreaSchool of Advanced Fusion Studies, University of Seoul, Seoul, South KoreaSchool of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon, South KoreaThe distinct advantages of low power consumption and hardware compactness make SAR ADCs especially appealing in scaled CMOS technologies, garnering significant attention. The residue left on the capacitor digital-to-analog converter (CDAC) after conversion in the SAR ADC negates the need for complex residue extraction circuits. This crucial feature has inspired numerous SAR-assisted architectural variations, employed in a range of applications from high resolution to high speed. This article introduces several energy-efficient hybrid ADC architectures that incorporate SAR ADCs as their sub blocks, including the following: SAR-assisted subranging SAR, which saves DAC switching power and can detect skew errors for time-interleaved ADCs; SAR-flash hybrid for energy-efficient high-speed conversion; SAR-assisted dual-residue pipelined ADC, which eliminates the stringent requirement for residue gain accuracy; and SAR-assisted delta–sigma modulator (DSM) with digital-domain noise coupling, which reduces the number of required analog integrators.https://ieeexplore.ieee.org/document/10702510/ADCdelta–sigma modulator (DSM) with digital noise coupling (DNC)flash-SARhybrid ADCspipelined-SARSAR ADC |
| spellingShingle | Kent Edrian Lozada Dong-Jin Chang Dong-Ryeol Oh Min-Jae Seo Seung-Tak Ryu SAR-Assisted Energy-Efficient Hybrid ADCs IEEE Open Journal of the Solid-State Circuits Society ADC delta–sigma modulator (DSM) with digital noise coupling (DNC) flash-SAR hybrid ADCs pipelined-SAR SAR ADC |
| title | SAR-Assisted Energy-Efficient Hybrid ADCs |
| title_full | SAR-Assisted Energy-Efficient Hybrid ADCs |
| title_fullStr | SAR-Assisted Energy-Efficient Hybrid ADCs |
| title_full_unstemmed | SAR-Assisted Energy-Efficient Hybrid ADCs |
| title_short | SAR-Assisted Energy-Efficient Hybrid ADCs |
| title_sort | sar assisted energy efficient hybrid adcs |
| topic | ADC delta–sigma modulator (DSM) with digital noise coupling (DNC) flash-SAR hybrid ADCs pipelined-SAR SAR ADC |
| url | https://ieeexplore.ieee.org/document/10702510/ |
| work_keys_str_mv | AT kentedrianlozada sarassistedenergyefficienthybridadcs AT dongjinchang sarassistedenergyefficienthybridadcs AT dongryeoloh sarassistedenergyefficienthybridadcs AT minjaeseo sarassistedenergyefficienthybridadcs AT seungtakryu sarassistedenergyefficienthybridadcs |