An SDR-Based GNSS-R CubeSat Payload: Hardware Development and Optimization of the Onboard Processing

Recent developments in high-performance Software Defined Radios (SDRs) and their utilization in CubeSat payloads are transforming Earth Observation (EO), including Microwave Radiometers, Global Navigation and Satellite System – Radio Occultations (GNSS-RO), and – Reflectometry...

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Bibliographic Details
Main Authors: Shah Zahid Khan, Yasir M. O. Abbas, Edwar Edwar, Abdul-Halim Jallad, Adriano Camps
Format: Article
Language:English
Published: IEEE 2025-01-01
Series:IEEE Access
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Online Access:https://ieeexplore.ieee.org/document/10906500/
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Summary:Recent developments in high-performance Software Defined Radios (SDRs) and their utilization in CubeSat payloads are transforming Earth Observation (EO), including Microwave Radiometers, Global Navigation and Satellite System – Radio Occultations (GNSS-RO), and – Reflectometry (GNSS-R). In recent years, GNSS-R has been increasingly used in land and marine environmental monitoring, with applications expanding to other emerging fields in EO. The so called Delay Doppler Map (DDM) is the primary observable of GNSS-R receivers, providing information on surface properties, i.e. dielectric constant and surface roughness. Efficient on-board processing is essential in CubeSat-based GNSS-R missions, due to the large volume of raw data and the constraints of limited downlink bandwidth. However, limited on-board computational resources present challenges, as DDM generation requires intensive Fast Fourier Transform (FFT) operations. This study presents the design and development of a cost-effective and compact 0.5U GNSS-R CubeSat payload that optimizes the GNSS-R data processing technique by using the auxiliary data from the reference signals, such as Pseudo-Random Noise (PRN) codes, and their Doppler frequencies in order to reduce the search space. This way the payload selectively processes the raw data, significantly reducing the computational load. The payload processing unit is implemented in Analog Devices ADRV9364 with a dual-core ARM Cortex-A9 processor with a Zynq-7000 Field-Programmable Gate Array (FPGA).
ISSN:2169-3536