Dual-Mode 2T1C DRAM Process-In-Memory Architecture for Boolean and MAC Operations
With the increasing demand for intelligent memory, the conventional memory system is more and more equipped with computational logic to support simple arithmetic and Boolean operations required by many real-world applications. Such a trend, called ‘Process-In-Memory’ architectu...
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| Format: | Article |
| Language: | English |
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IEEE
2025-01-01
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| Series: | IEEE Access |
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| Online Access: | https://ieeexplore.ieee.org/document/11095698/ |
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| author | Yerim An Honggu Kim Dongjun Son Hakrae Yu Yong Shim |
| author_facet | Yerim An Honggu Kim Dongjun Son Hakrae Yu Yong Shim |
| author_sort | Yerim An |
| collection | DOAJ |
| description | With the increasing demand for intelligent memory, the conventional memory system is more and more equipped with computational logic to support simple arithmetic and Boolean operations required by many real-world applications. Such a trend, called ‘Process-In-Memory’ architecture, tries to utilize most of the memory candidates ranging from the conventional charge-based memory such as SRAM, DRAM, and Flash to the emerging memory devices such as RRAM, PRAM and MRAM. From the application perspective, many researchers are putting efforts to develop efficient memory peripherals with CMOS circuits to support one of two operations: 1) Boolean function, and 2) simple arithmetic operations such as multiplication and accumulation (addition), which is typically referred to as MAC operation. However, there are not many previous works that support both operations in a single system. In this article, we propose a 2T1C DRAM-based PIM architecture that supports dual-mode operation with minimal additional hardware. The proposed architecture has been fabricated using a commercial 65nm CMOS technology and successfully proves that the target operations are performed with a reasonably good accuracy. |
| format | Article |
| id | doaj-art-22d0afb6f9b644b4a6a23c823b22f338 |
| institution | DOAJ |
| issn | 2169-3536 |
| language | English |
| publishDate | 2025-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj-art-22d0afb6f9b644b4a6a23c823b22f3382025-08-20T03:22:19ZengIEEEIEEE Access2169-35362025-01-011313392513393610.1109/ACCESS.2025.359235211095698Dual-Mode 2T1C DRAM Process-In-Memory Architecture for Boolean and MAC OperationsYerim An0https://orcid.org/0009-0008-8939-2368Honggu Kim1https://orcid.org/0009-0007-1306-2824Dongjun Son2https://orcid.org/0009-0000-2897-2600Hakrae Yu3Yong Shim4https://orcid.org/0000-0002-7101-6718Department of Intelligent Semiconductor Engineering, Chung-Ang University, Dongjak-gu, Seoul, Republic of KoreaDepartment of Intelligent Semiconductor Engineering, Chung-Ang University, Dongjak-gu, Seoul, Republic of KoreaDepartment of Intelligent Semiconductor Engineering, Chung-Ang University, Dongjak-gu, Seoul, Republic of KoreaDepartment of Intelligent Semiconductor Engineering, Chung-Ang University, Dongjak-gu, Seoul, Republic of KoreaDepartment of Intelligent Semiconductor Engineering, Chung-Ang University, Dongjak-gu, Seoul, Republic of KoreaWith the increasing demand for intelligent memory, the conventional memory system is more and more equipped with computational logic to support simple arithmetic and Boolean operations required by many real-world applications. Such a trend, called ‘Process-In-Memory’ architecture, tries to utilize most of the memory candidates ranging from the conventional charge-based memory such as SRAM, DRAM, and Flash to the emerging memory devices such as RRAM, PRAM and MRAM. From the application perspective, many researchers are putting efforts to develop efficient memory peripherals with CMOS circuits to support one of two operations: 1) Boolean function, and 2) simple arithmetic operations such as multiplication and accumulation (addition), which is typically referred to as MAC operation. However, there are not many previous works that support both operations in a single system. In this article, we propose a 2T1C DRAM-based PIM architecture that supports dual-mode operation with minimal additional hardware. The proposed architecture has been fabricated using a commercial 65nm CMOS technology and successfully proves that the target operations are performed with a reasonably good accuracy.https://ieeexplore.ieee.org/document/11095698/Processing-in-memory (PIM)DRAMDRAM compute-in-memoryDNN acceleratordual mode operationBoolean function |
| spellingShingle | Yerim An Honggu Kim Dongjun Son Hakrae Yu Yong Shim Dual-Mode 2T1C DRAM Process-In-Memory Architecture for Boolean and MAC Operations IEEE Access Processing-in-memory (PIM) DRAM DRAM compute-in-memory DNN accelerator dual mode operation Boolean function |
| title | Dual-Mode 2T1C DRAM Process-In-Memory Architecture for Boolean and MAC Operations |
| title_full | Dual-Mode 2T1C DRAM Process-In-Memory Architecture for Boolean and MAC Operations |
| title_fullStr | Dual-Mode 2T1C DRAM Process-In-Memory Architecture for Boolean and MAC Operations |
| title_full_unstemmed | Dual-Mode 2T1C DRAM Process-In-Memory Architecture for Boolean and MAC Operations |
| title_short | Dual-Mode 2T1C DRAM Process-In-Memory Architecture for Boolean and MAC Operations |
| title_sort | dual mode 2t1c dram process in memory architecture for boolean and mac operations |
| topic | Processing-in-memory (PIM) DRAM DRAM compute-in-memory DNN accelerator dual mode operation Boolean function |
| url | https://ieeexplore.ieee.org/document/11095698/ |
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