Novel Frame Buffer Pixel Circuits and Silicon Backplane Development for Polarization-Independent LCOS
This project aims to develop novel frame buffer pixel circuit-based silicon backplanes using 180 nm process technology for polarization-independent liquid crystal on silicon (PI-LCOS) phase modulators. Three unique pixel circuits, which exclusively utilize NMOS transistors, have been designed to min...
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| Format: | Article |
| Language: | English |
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IEEE
2024-01-01
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| Series: | IEEE Photonics Journal |
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| Online Access: | https://ieeexplore.ieee.org/document/10682515/ |
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| _version_ | 1849415885016530944 |
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| author | Qirui Zhang Isaac Zachmann Lianhua Ji Chongchang Mao |
| author_facet | Qirui Zhang Isaac Zachmann Lianhua Ji Chongchang Mao |
| author_sort | Qirui Zhang |
| collection | DOAJ |
| description | This project aims to develop novel frame buffer pixel circuit-based silicon backplanes using 180 nm process technology for polarization-independent liquid crystal on silicon (PI-LCOS) phase modulators. Three unique pixel circuits, which exclusively utilize NMOS transistors, have been designed to minimize pixel size and improve production yield. Additionally, the "Voltage Booster” (VBOOST) technique extends the dynamic voltage range, crucial for stable phase modulation and high grayscale. Efforts are also underway to enhance stability against voltage fluctuation by incorporating the auxiliary capacitor or refined active-driving pixel-electrode stage. The prototype silicon backplane features a 64 × 64-pixel matrix with column and row decoders for individual pixel addressing, facilitating optical testing. By employing a two-stage analog dynamic random-access memory (DRAM), the pixel circuit supports sequential data loading row by row throughout the array while simultaneously displaying previously loaded frame data. This ‘frame-at-a-time’ data refresh capability is vital for displaying images with full contrast, which is particularly advantageous for holographic and color sequential display applications. Simulation and experimental assessments on the silicon backplane chips demonstrate that these pixel circuits can support a high-resolution LCOS device with approximately 4.15 um x 4.15 um pixel pitch in the 180 nm process technology, a high voltage holding ratio exceeding 94%, and substantial grayscale modulation depth. |
| format | Article |
| id | doaj-art-1dcb96a5f6fc4bebadb02f1e53fec1dc |
| institution | Kabale University |
| issn | 1943-0655 |
| language | English |
| publishDate | 2024-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Photonics Journal |
| spelling | doaj-art-1dcb96a5f6fc4bebadb02f1e53fec1dc2025-08-20T03:33:21ZengIEEEIEEE Photonics Journal1943-06552024-01-011651910.1109/JPHOT.2024.346288910682515Novel Frame Buffer Pixel Circuits and Silicon Backplane Development for Polarization-Independent LCOSQirui Zhang0https://orcid.org/0009-0007-0572-5763Isaac Zachmann1https://orcid.org/0009-0002-7076-8421Lianhua Ji2https://orcid.org/0000-0001-6683-5666Chongchang Mao3https://orcid.org/0009-0007-2234-5797Electrical and Computer Engineering Department, ElectroScience Laboratory, Columbus, OH, USAElectrical and Computer Engineering Department, ElectroScience Laboratory, Columbus, OH, USAElectrical and Computer Engineering Department, ElectroScience Laboratory, Columbus, OH, USAElectrical and Computer Engineering Department, ElectroScience Laboratory, Columbus, OH, USAThis project aims to develop novel frame buffer pixel circuit-based silicon backplanes using 180 nm process technology for polarization-independent liquid crystal on silicon (PI-LCOS) phase modulators. Three unique pixel circuits, which exclusively utilize NMOS transistors, have been designed to minimize pixel size and improve production yield. Additionally, the "Voltage Booster” (VBOOST) technique extends the dynamic voltage range, crucial for stable phase modulation and high grayscale. Efforts are also underway to enhance stability against voltage fluctuation by incorporating the auxiliary capacitor or refined active-driving pixel-electrode stage. The prototype silicon backplane features a 64 × 64-pixel matrix with column and row decoders for individual pixel addressing, facilitating optical testing. By employing a two-stage analog dynamic random-access memory (DRAM), the pixel circuit supports sequential data loading row by row throughout the array while simultaneously displaying previously loaded frame data. This ‘frame-at-a-time’ data refresh capability is vital for displaying images with full contrast, which is particularly advantageous for holographic and color sequential display applications. Simulation and experimental assessments on the silicon backplane chips demonstrate that these pixel circuits can support a high-resolution LCOS device with approximately 4.15 um x 4.15 um pixel pitch in the 180 nm process technology, a high voltage holding ratio exceeding 94%, and substantial grayscale modulation depth.https://ieeexplore.ieee.org/document/10682515/Frame buffer pixel circuitliquid crystal on silicon (LCOS)high pixel per inch (PPI)micro-display |
| spellingShingle | Qirui Zhang Isaac Zachmann Lianhua Ji Chongchang Mao Novel Frame Buffer Pixel Circuits and Silicon Backplane Development for Polarization-Independent LCOS IEEE Photonics Journal Frame buffer pixel circuit liquid crystal on silicon (LCOS) high pixel per inch (PPI) micro-display |
| title | Novel Frame Buffer Pixel Circuits and Silicon Backplane Development for Polarization-Independent LCOS |
| title_full | Novel Frame Buffer Pixel Circuits and Silicon Backplane Development for Polarization-Independent LCOS |
| title_fullStr | Novel Frame Buffer Pixel Circuits and Silicon Backplane Development for Polarization-Independent LCOS |
| title_full_unstemmed | Novel Frame Buffer Pixel Circuits and Silicon Backplane Development for Polarization-Independent LCOS |
| title_short | Novel Frame Buffer Pixel Circuits and Silicon Backplane Development for Polarization-Independent LCOS |
| title_sort | novel frame buffer pixel circuits and silicon backplane development for polarization independent lcos |
| topic | Frame buffer pixel circuit liquid crystal on silicon (LCOS) high pixel per inch (PPI) micro-display |
| url | https://ieeexplore.ieee.org/document/10682515/ |
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