Cachedia: An Environment for Efficient Cache Verification With Graphic Visualization for Debugging

The recent boom in open-source processor architectures such as RISC-V has increased the never-ending demand for peripherals and System-on-Chip (SoC) hardware. With this in mind, how to provide an efficient graphical interface environment to increase the visibility of this system is an important ques...

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Main Authors: Francisco J. Rodriguez-Navarrete, German Pinedo-Diaz, L. A. Luna-Rodriguez, Susana Ortega-Cisneros, L. Pizano-Escalante, J. J. Raygoza-Panduro
Format: Article
Language:English
Published: IEEE 2025-01-01
Series:IEEE Access
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Online Access:https://ieeexplore.ieee.org/document/10847810/
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author Francisco J. Rodriguez-Navarrete
German Pinedo-Diaz
L. A. Luna-Rodriguez
Susana Ortega-Cisneros
L. Pizano-Escalante
J. J. Raygoza-Panduro
author_facet Francisco J. Rodriguez-Navarrete
German Pinedo-Diaz
L. A. Luna-Rodriguez
Susana Ortega-Cisneros
L. Pizano-Escalante
J. J. Raygoza-Panduro
author_sort Francisco J. Rodriguez-Navarrete
collection DOAJ
description The recent boom in open-source processor architectures such as RISC-V has increased the never-ending demand for peripherals and System-on-Chip (SoC) hardware. With this in mind, how to provide an efficient graphical interface environment to increase the visibility of this system is an important question, not only for processors but also for internal blocks such as caches. This paper introduces Cachedia as an environment for better visualization and debugging of direct-mapped and set-associative hardware caches using graphical interfaces. Cachedia provides a comprehensive and user-friendly environment for designing, debugging, and verifying these systems for a variety of applications. The tool includes a Graphical User Interface (GUI) that allows the user to not only configure, visualize and understand the behavior of a cache but also to create an abstract model view to verify the provided hardware design. This provides a visual method for learning and understanding the system and the tools for further development and verification. The environment successfully generated a view model for a configurable cache that can be instantiated as a block design in Vivado. In summary, using the graphic visualization blocks in Cachedia can potentially be advantageous for debugging complex hardware designs.
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publishDate 2025-01-01
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spelling doaj-art-1cc9ec83e353471dbb6c3bfeb53e3de02025-08-20T03:07:28ZengIEEEIEEE Access2169-35362025-01-0113938409385110.1109/ACCESS.2025.353189710847810Cachedia: An Environment for Efficient Cache Verification With Graphic Visualization for DebuggingFrancisco J. Rodriguez-Navarrete0https://orcid.org/0000-0001-6871-3611German Pinedo-Diaz1https://orcid.org/0000-0003-4802-6632L. A. Luna-Rodriguez2Susana Ortega-Cisneros3https://orcid.org/0000-0001-6646-1529L. Pizano-Escalante4https://orcid.org/0000-0001-7034-8967J. J. Raygoza-Panduro5https://orcid.org/0000-0002-8567-4981Center for Research and Advanced Studies of the National Polytechnic Institute (CINVESTAV), Guadalajara Campus, Zapopan, MexicoCenter for Research and Advanced Studies of the National Polytechnic Institute (CINVESTAV), Guadalajara Campus, Zapopan, MexicoUniversidad Internacional de la Rioja (UNIR), México Campus, Mexico City, MexicoCenter for Research and Advanced Studies of the National Polytechnic Institute (CINVESTAV), Guadalajara Campus, Zapopan, MexicoSystems and IT Department, Electronics, ITESO University, San Pedro Tlaquepaque, MexicoDepartment of Electrophotonics, Division of Technologies for Cyber Human Integration, UDG, Guadalajara, MexicoThe recent boom in open-source processor architectures such as RISC-V has increased the never-ending demand for peripherals and System-on-Chip (SoC) hardware. With this in mind, how to provide an efficient graphical interface environment to increase the visibility of this system is an important question, not only for processors but also for internal blocks such as caches. This paper introduces Cachedia as an environment for better visualization and debugging of direct-mapped and set-associative hardware caches using graphical interfaces. Cachedia provides a comprehensive and user-friendly environment for designing, debugging, and verifying these systems for a variety of applications. The tool includes a Graphical User Interface (GUI) that allows the user to not only configure, visualize and understand the behavior of a cache but also to create an abstract model view to verify the provided hardware design. This provides a visual method for learning and understanding the system and the tools for further development and verification. The environment successfully generated a view model for a configurable cache that can be instantiated as a block design in Vivado. In summary, using the graphic visualization blocks in Cachedia can potentially be advantageous for debugging complex hardware designs.https://ieeexplore.ieee.org/document/10847810/Cache systemsvisualization modelsGUIhardware visual representationvisual debugging
spellingShingle Francisco J. Rodriguez-Navarrete
German Pinedo-Diaz
L. A. Luna-Rodriguez
Susana Ortega-Cisneros
L. Pizano-Escalante
J. J. Raygoza-Panduro
Cachedia: An Environment for Efficient Cache Verification With Graphic Visualization for Debugging
IEEE Access
Cache systems
visualization models
GUI
hardware visual representation
visual debugging
title Cachedia: An Environment for Efficient Cache Verification With Graphic Visualization for Debugging
title_full Cachedia: An Environment for Efficient Cache Verification With Graphic Visualization for Debugging
title_fullStr Cachedia: An Environment for Efficient Cache Verification With Graphic Visualization for Debugging
title_full_unstemmed Cachedia: An Environment for Efficient Cache Verification With Graphic Visualization for Debugging
title_short Cachedia: An Environment for Efficient Cache Verification With Graphic Visualization for Debugging
title_sort cachedia an environment for efficient cache verification with graphic visualization for debugging
topic Cache systems
visualization models
GUI
hardware visual representation
visual debugging
url https://ieeexplore.ieee.org/document/10847810/
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AT lalunarodriguez cachediaanenvironmentforefficientcacheverificationwithgraphicvisualizationfordebugging
AT susanaortegacisneros cachediaanenvironmentforefficientcacheverificationwithgraphicvisualizationfordebugging
AT lpizanoescalante cachediaanenvironmentforefficientcacheverificationwithgraphicvisualizationfordebugging
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