Optimizing Instruction Scheduling and Register Allocation for Register-File-Connected Clustered VLIW Architectures
Clustering has become a common trend in very long instruction words (VLIW) architecture to solve the problem of area, energy consumption, and design complexity. Register-file-connected clustered (RFCC) VLIW architecture uses the mechanism of global register file to accomplish the inter-cluster data...
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| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
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Wiley
2013-01-01
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| Series: | The Scientific World Journal |
| Online Access: | http://dx.doi.org/10.1155/2013/913038 |
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| author | Haijing Tang Xu Yang Siye Wang Yanjun Zhang |
| author_facet | Haijing Tang Xu Yang Siye Wang Yanjun Zhang |
| author_sort | Haijing Tang |
| collection | DOAJ |
| description | Clustering has become a common trend in very long instruction words (VLIW) architecture to solve the problem of area, energy consumption, and design complexity. Register-file-connected clustered (RFCC) VLIW architecture uses the mechanism of global register file to accomplish the inter-cluster data communications, thus eliminating the performance and energy consumption penalty caused by explicit inter-cluster data move operations in traditional bus-connected clustered (BCC) VLIW architecture. However, the limit number of access ports to the global register file has become an issue which must be well addressed; otherwise the performance and energy consumption would be harmed. In this paper, we presented compiler optimization techniques for an RFCC VLIW architecture called Lily, which is designed for encryption systems. These techniques aim at optimizing performance and energy consumption for Lily architecture, through appropriate manipulation of the code generation process to maintain a better management of the accesses to the global register file. All the techniques have been implemented and evaluated. The result shows that our techniques can significantly reduce the penalty of performance and energy consumption due to access port limitation of global register file. |
| format | Article |
| id | doaj-art-1c09116f84d741b8a8b1ade091d22df0 |
| institution | Kabale University |
| issn | 1537-744X |
| language | English |
| publishDate | 2013-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | The Scientific World Journal |
| spelling | doaj-art-1c09116f84d741b8a8b1ade091d22df02025-08-20T03:54:38ZengWileyThe Scientific World Journal1537-744X2013-01-01201310.1155/2013/913038913038Optimizing Instruction Scheduling and Register Allocation for Register-File-Connected Clustered VLIW ArchitecturesHaijing Tang0Xu Yang1Siye Wang2Yanjun Zhang3School of Software, Beijing Institute of Technology, Beijing, ChinaSchool of Software, Beijing Institute of Technology, Beijing, ChinaSchool of Information and Electronics, Beijing Institute of Technology, Beijing, ChinaSchool of Information and Electronics, Beijing Institute of Technology, Beijing, ChinaClustering has become a common trend in very long instruction words (VLIW) architecture to solve the problem of area, energy consumption, and design complexity. Register-file-connected clustered (RFCC) VLIW architecture uses the mechanism of global register file to accomplish the inter-cluster data communications, thus eliminating the performance and energy consumption penalty caused by explicit inter-cluster data move operations in traditional bus-connected clustered (BCC) VLIW architecture. However, the limit number of access ports to the global register file has become an issue which must be well addressed; otherwise the performance and energy consumption would be harmed. In this paper, we presented compiler optimization techniques for an RFCC VLIW architecture called Lily, which is designed for encryption systems. These techniques aim at optimizing performance and energy consumption for Lily architecture, through appropriate manipulation of the code generation process to maintain a better management of the accesses to the global register file. All the techniques have been implemented and evaluated. The result shows that our techniques can significantly reduce the penalty of performance and energy consumption due to access port limitation of global register file.http://dx.doi.org/10.1155/2013/913038 |
| spellingShingle | Haijing Tang Xu Yang Siye Wang Yanjun Zhang Optimizing Instruction Scheduling and Register Allocation for Register-File-Connected Clustered VLIW Architectures The Scientific World Journal |
| title | Optimizing Instruction Scheduling and Register Allocation for Register-File-Connected Clustered VLIW Architectures |
| title_full | Optimizing Instruction Scheduling and Register Allocation for Register-File-Connected Clustered VLIW Architectures |
| title_fullStr | Optimizing Instruction Scheduling and Register Allocation for Register-File-Connected Clustered VLIW Architectures |
| title_full_unstemmed | Optimizing Instruction Scheduling and Register Allocation for Register-File-Connected Clustered VLIW Architectures |
| title_short | Optimizing Instruction Scheduling and Register Allocation for Register-File-Connected Clustered VLIW Architectures |
| title_sort | optimizing instruction scheduling and register allocation for register file connected clustered vliw architectures |
| url | http://dx.doi.org/10.1155/2013/913038 |
| work_keys_str_mv | AT haijingtang optimizinginstructionschedulingandregisterallocationforregisterfileconnectedclusteredvliwarchitectures AT xuyang optimizinginstructionschedulingandregisterallocationforregisterfileconnectedclusteredvliwarchitectures AT siyewang optimizinginstructionschedulingandregisterallocationforregisterfileconnectedclusteredvliwarchitectures AT yanjunzhang optimizinginstructionschedulingandregisterallocationforregisterfileconnectedclusteredvliwarchitectures |