Novel Trade-offs in 5 nm FinFET SRAM Arrays at Extremely Low Temperatures
Complementary metal–oxide–semiconductor (CMOS)-based computing promises drastic improvement in performance at extremely low temperatures (e.g., 77 K, 10 K). The field of extremely low temperature CMOS-environment-based computing holds the promise of delivering remarkable enhanc...
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IEEE
2025-01-01
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| Series: | IEEE Transactions on Quantum Engineering |
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| Online Access: | https://ieeexplore.ieee.org/document/10778409/ |
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| author | Shivendra Singh Parihar Girish Pahwa Baker Mohammad Yogesh Singh Chauhan Hussam Amrouch |
| author_facet | Shivendra Singh Parihar Girish Pahwa Baker Mohammad Yogesh Singh Chauhan Hussam Amrouch |
| author_sort | Shivendra Singh Parihar |
| collection | DOAJ |
| description | Complementary metal–oxide–semiconductor (CMOS)-based computing promises drastic improvement in performance at extremely low temperatures (e.g., 77 K, 10 K). The field of extremely low temperature CMOS-environment-based computing holds the promise of delivering remarkable enhancements in both performance and power consumption. Static random access memory (SRAM) plays a major role in determining the performance and efficiency of any processor due to its superior performance and density. This work aims to reveal how extremely low temperature operations profoundly impact the existing well-known tradeoffs in SRAM-based memory arrays. To accomplish this, first, we measure and model the 5 nm fin field-effect transistors characteristics over a wide temperature range from 300 K down to 10 K. Next, we develop a framework to perform simulations on the SRAM array by varying the number of rows and columns for examining the influence of leakage current (<inline-formula><tex-math notation="LaTeX">$I$</tex-math></inline-formula><sub>leak</sub>) and parasitic effects of bit line (BL) and word line (WL) on the size and performance of the SRAM array under extremely low temperatures. For a comprehensive analysis, we further investigated the maximum attainable array size, extending our study down to 10 K, utilizing three distinct cell types. With the help of SRAM array simulations, we reveal that the maximum array size at extremely low temperatures is limited by WL parasitics instead of <inline-formula><tex-math notation="LaTeX">$I$</tex-math></inline-formula><sub>leak</sub>, and the performance of the SRAM is governed by BL and WL parasitics. In addition, we elucidate the influence of transistor threshold voltage (<inline-formula><tex-math notation="LaTeX">$V$</tex-math></inline-formula><sub>TH</sub>) engineering on the optimization of the SRAM array at extremely low temperature environments. |
| format | Article |
| id | doaj-art-1bc90249ebf9453b998eeb974d52f761 |
| institution | Kabale University |
| issn | 2689-1808 |
| language | English |
| publishDate | 2025-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Transactions on Quantum Engineering |
| spelling | doaj-art-1bc90249ebf9453b998eeb974d52f7612025-01-14T00:03:02ZengIEEEIEEE Transactions on Quantum Engineering2689-18082025-01-01611510.1109/TQE.2024.351236710778409Novel Trade-offs in 5 nm FinFET SRAM Arrays at Extremely Low TemperaturesShivendra Singh Parihar0https://orcid.org/0000-0001-7104-2396Girish Pahwa1https://orcid.org/0000-0003-2094-858XBaker Mohammad2https://orcid.org/0000-0002-6063-473XYogesh Singh Chauhan3https://orcid.org/0000-0002-3356-8917Hussam Amrouch4https://orcid.org/0000-0002-5649-3102Chair of Semiconductor Test and Reliability, University of Stuttgart, Stuttgart, GermanyInternational College of Semiconductor Technology, National Yang Ming Chiao Tung University, Hsinchu, TaiwanDepartment of Electrical Engineering and Computer Science, System on Chip Center, Khalifa University, Abu Dhabi, United Arab EmiratesNanolab, Department of Electrical Engineering, Indian Institute of Technology Kanpur, Kanpur, IndiaTUM School of Computation, Information and Technology, Chair of AI Processor Design, Munich Institute of Robotics and Machine Intelligence, Technical University of Munich, Munich, GermanyComplementary metal–oxide–semiconductor (CMOS)-based computing promises drastic improvement in performance at extremely low temperatures (e.g., 77 K, 10 K). The field of extremely low temperature CMOS-environment-based computing holds the promise of delivering remarkable enhancements in both performance and power consumption. Static random access memory (SRAM) plays a major role in determining the performance and efficiency of any processor due to its superior performance and density. This work aims to reveal how extremely low temperature operations profoundly impact the existing well-known tradeoffs in SRAM-based memory arrays. To accomplish this, first, we measure and model the 5 nm fin field-effect transistors characteristics over a wide temperature range from 300 K down to 10 K. Next, we develop a framework to perform simulations on the SRAM array by varying the number of rows and columns for examining the influence of leakage current (<inline-formula><tex-math notation="LaTeX">$I$</tex-math></inline-formula><sub>leak</sub>) and parasitic effects of bit line (BL) and word line (WL) on the size and performance of the SRAM array under extremely low temperatures. For a comprehensive analysis, we further investigated the maximum attainable array size, extending our study down to 10 K, utilizing three distinct cell types. With the help of SRAM array simulations, we reveal that the maximum array size at extremely low temperatures is limited by WL parasitics instead of <inline-formula><tex-math notation="LaTeX">$I$</tex-math></inline-formula><sub>leak</sub>, and the performance of the SRAM is governed by BL and WL parasitics. In addition, we elucidate the influence of transistor threshold voltage (<inline-formula><tex-math notation="LaTeX">$V$</tex-math></inline-formula><sub>TH</sub>) engineering on the optimization of the SRAM array at extremely low temperature environments.https://ieeexplore.ieee.org/document/10778409/5 nm fin field-effect transistor (FinFET)cryogenic complementary metal–oxide–semiconductor (CMOS)low-power designmemory optimizationstatic random access memory (SRAM) |
| spellingShingle | Shivendra Singh Parihar Girish Pahwa Baker Mohammad Yogesh Singh Chauhan Hussam Amrouch Novel Trade-offs in 5 nm FinFET SRAM Arrays at Extremely Low Temperatures IEEE Transactions on Quantum Engineering 5 nm fin field-effect transistor (FinFET) cryogenic complementary metal–oxide–semiconductor (CMOS) low-power design memory optimization static random access memory (SRAM) |
| title | Novel Trade-offs in 5 nm FinFET SRAM Arrays at Extremely Low Temperatures |
| title_full | Novel Trade-offs in 5 nm FinFET SRAM Arrays at Extremely Low Temperatures |
| title_fullStr | Novel Trade-offs in 5 nm FinFET SRAM Arrays at Extremely Low Temperatures |
| title_full_unstemmed | Novel Trade-offs in 5 nm FinFET SRAM Arrays at Extremely Low Temperatures |
| title_short | Novel Trade-offs in 5 nm FinFET SRAM Arrays at Extremely Low Temperatures |
| title_sort | novel trade offs in 5 nm finfet sram arrays at extremely low temperatures |
| topic | 5 nm fin field-effect transistor (FinFET) cryogenic complementary metal–oxide–semiconductor (CMOS) low-power design memory optimization static random access memory (SRAM) |
| url | https://ieeexplore.ieee.org/document/10778409/ |
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