Efficient Execution of Networked MPSoC Models by Exploiting Multiple Platform Levels
Novel embedded applications are characterized by increasing requirements on processing performance as well as the demand for communication between several or many devices. Networked Multiprocessor System-on-Chips (MPSoCs) are a possible solution to cope with this increasing complexity. Such systems...
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| Main Authors: | , , , , |
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| Format: | Article |
| Language: | English |
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Wiley
2012-01-01
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| Series: | International Journal of Reconfigurable Computing |
| Online Access: | http://dx.doi.org/10.1155/2012/729786 |
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| _version_ | 1850236403406864384 |
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| author | Christoph Roth Joachim Meyer Michael Rückauer Oliver Sander Jürgen Becker |
| author_facet | Christoph Roth Joachim Meyer Michael Rückauer Oliver Sander Jürgen Becker |
| author_sort | Christoph Roth |
| collection | DOAJ |
| description | Novel embedded applications are characterized by increasing requirements on processing performance as well as the demand for communication between several or many devices. Networked Multiprocessor System-on-Chips (MPSoCs) are a possible solution to cope with this increasing complexity. Such systems require a detailed exploration on both architectures and system design. An approach that allows investigating interdependencies between system and network domain is the cooperative execution of system design tools with a network simulator. Within previous work, synchronization mechanisms have been developed for parallel system simulation and system/network co-simulation using the high level architecture (HLA). Within this contribution, a methodology is presented that extends previous work with further building blocks towards a construction kit for system/network co-simulation. The methodology facilitates flexible assembly of components and adaptation to the specific needs of use cases in terms of performance and accuracy. Underlying concepts and made extensions are discussed in detail. Benefits are substantiated by means of various benchmarks. |
| format | Article |
| id | doaj-art-1aa77d314a4148bcbe476e4d6af60406 |
| institution | OA Journals |
| issn | 1687-7195 1687-7209 |
| language | English |
| publishDate | 2012-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | International Journal of Reconfigurable Computing |
| spelling | doaj-art-1aa77d314a4148bcbe476e4d6af604062025-08-20T02:01:58ZengWileyInternational Journal of Reconfigurable Computing1687-71951687-72092012-01-01201210.1155/2012/729786729786Efficient Execution of Networked MPSoC Models by Exploiting Multiple Platform LevelsChristoph Roth0Joachim Meyer1Michael Rückauer2Oliver Sander3Jürgen Becker4Karlsruhe Institute of Technology (KIT), Institute for Information Processing Technology (ITIV), 76131 Karlsruhe, GermanyKarlsruhe Institute of Technology (KIT), Institute for Information Processing Technology (ITIV), 76131 Karlsruhe, GermanyKarlsruhe Institute of Technology (KIT), Institute for Information Processing Technology (ITIV), 76131 Karlsruhe, GermanyKarlsruhe Institute of Technology (KIT), Institute for Information Processing Technology (ITIV), 76131 Karlsruhe, GermanyKarlsruhe Institute of Technology (KIT), Institute for Information Processing Technology (ITIV), 76131 Karlsruhe, GermanyNovel embedded applications are characterized by increasing requirements on processing performance as well as the demand for communication between several or many devices. Networked Multiprocessor System-on-Chips (MPSoCs) are a possible solution to cope with this increasing complexity. Such systems require a detailed exploration on both architectures and system design. An approach that allows investigating interdependencies between system and network domain is the cooperative execution of system design tools with a network simulator. Within previous work, synchronization mechanisms have been developed for parallel system simulation and system/network co-simulation using the high level architecture (HLA). Within this contribution, a methodology is presented that extends previous work with further building blocks towards a construction kit for system/network co-simulation. The methodology facilitates flexible assembly of components and adaptation to the specific needs of use cases in terms of performance and accuracy. Underlying concepts and made extensions are discussed in detail. Benefits are substantiated by means of various benchmarks.http://dx.doi.org/10.1155/2012/729786 |
| spellingShingle | Christoph Roth Joachim Meyer Michael Rückauer Oliver Sander Jürgen Becker Efficient Execution of Networked MPSoC Models by Exploiting Multiple Platform Levels International Journal of Reconfigurable Computing |
| title | Efficient Execution of Networked MPSoC Models by Exploiting Multiple Platform Levels |
| title_full | Efficient Execution of Networked MPSoC Models by Exploiting Multiple Platform Levels |
| title_fullStr | Efficient Execution of Networked MPSoC Models by Exploiting Multiple Platform Levels |
| title_full_unstemmed | Efficient Execution of Networked MPSoC Models by Exploiting Multiple Platform Levels |
| title_short | Efficient Execution of Networked MPSoC Models by Exploiting Multiple Platform Levels |
| title_sort | efficient execution of networked mpsoc models by exploiting multiple platform levels |
| url | http://dx.doi.org/10.1155/2012/729786 |
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