Hierarchical memories: Simulating quantum LDPC codes with local gates
Constant-rate low-density parity-check (LDPC) codes are promising candidates for constructing efficient fault-tolerant quantum memories. However, if physical gates are subject to geometric-locality constraints, it becomes challenging to realize these codes. In this paper, we construct a new family o...
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Verein zur Förderung des Open Access Publizierens in den Quantenwissenschaften
2025-05-01
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| Series: | Quantum |
| Online Access: | https://quantum-journal.org/papers/q-2025-05-05-1728/pdf/ |
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| author | Christopher A. Pattison Anirudh Krishna John Preskill |
| author_facet | Christopher A. Pattison Anirudh Krishna John Preskill |
| author_sort | Christopher A. Pattison |
| collection | DOAJ |
| description | Constant-rate low-density parity-check (LDPC) codes are promising candidates for constructing efficient fault-tolerant quantum memories. However, if physical gates are subject to geometric-locality constraints, it becomes challenging to realize these codes. In this paper, we construct a new family of $[[N,K,D]]$ codes, referred to as hierarchical codes, that encode a number of logical qubits $K = \Omega(N/\log(N)^2)$. The $N^{th}$ element of this code family is obtained by concatenating a constant-rate quantum LDPC code with a surface code; nearest-neighbor gates in two dimensions are sufficient to implement the corresponding syndrome-extraction circuit and achieve a threshold. Below threshold the logical failure rate vanishes superpolynomially as a function of the distance $D(N)$. We present a bilayer architecture for implementing the syndrome-extraction circuit, and estimate the logical failure rate for this architecture. Under conservative assumptions, we find that the hierarchical code outperforms the basic encoding where all logical qubits are encoded in the surface code. |
| format | Article |
| id | doaj-art-19b695994d77435ebc0df0c5c87abd8a |
| institution | OA Journals |
| issn | 2521-327X |
| language | English |
| publishDate | 2025-05-01 |
| publisher | Verein zur Förderung des Open Access Publizierens in den Quantenwissenschaften |
| record_format | Article |
| series | Quantum |
| spelling | doaj-art-19b695994d77435ebc0df0c5c87abd8a2025-08-20T02:11:25ZengVerein zur Förderung des Open Access Publizierens in den QuantenwissenschaftenQuantum2521-327X2025-05-019172810.22331/q-2025-05-05-172810.22331/q-2025-05-05-1728Hierarchical memories: Simulating quantum LDPC codes with local gatesChristopher A. PattisonAnirudh KrishnaJohn PreskillConstant-rate low-density parity-check (LDPC) codes are promising candidates for constructing efficient fault-tolerant quantum memories. However, if physical gates are subject to geometric-locality constraints, it becomes challenging to realize these codes. In this paper, we construct a new family of $[[N,K,D]]$ codes, referred to as hierarchical codes, that encode a number of logical qubits $K = \Omega(N/\log(N)^2)$. The $N^{th}$ element of this code family is obtained by concatenating a constant-rate quantum LDPC code with a surface code; nearest-neighbor gates in two dimensions are sufficient to implement the corresponding syndrome-extraction circuit and achieve a threshold. Below threshold the logical failure rate vanishes superpolynomially as a function of the distance $D(N)$. We present a bilayer architecture for implementing the syndrome-extraction circuit, and estimate the logical failure rate for this architecture. Under conservative assumptions, we find that the hierarchical code outperforms the basic encoding where all logical qubits are encoded in the surface code.https://quantum-journal.org/papers/q-2025-05-05-1728/pdf/ |
| spellingShingle | Christopher A. Pattison Anirudh Krishna John Preskill Hierarchical memories: Simulating quantum LDPC codes with local gates Quantum |
| title | Hierarchical memories: Simulating quantum LDPC codes with local gates |
| title_full | Hierarchical memories: Simulating quantum LDPC codes with local gates |
| title_fullStr | Hierarchical memories: Simulating quantum LDPC codes with local gates |
| title_full_unstemmed | Hierarchical memories: Simulating quantum LDPC codes with local gates |
| title_short | Hierarchical memories: Simulating quantum LDPC codes with local gates |
| title_sort | hierarchical memories simulating quantum ldpc codes with local gates |
| url | https://quantum-journal.org/papers/q-2025-05-05-1728/pdf/ |
| work_keys_str_mv | AT christopherapattison hierarchicalmemoriessimulatingquantumldpccodeswithlocalgates AT anirudhkrishna hierarchicalmemoriessimulatingquantumldpccodeswithlocalgates AT johnpreskill hierarchicalmemoriessimulatingquantumldpccodeswithlocalgates |