Design of a VLSI Decoder for Partially Structured LDPC Codes
The starting point of this work is the development of a new class of partially structured LDPC codes, very well suited for hardware implementation. Specifically these codes are built so that the edges of their parity matrix can be partitioned into two disjoint sets, namely, the structured and the ra...
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| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
Wiley
2008-01-01
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| Series: | International Journal of Digital Multimedia Broadcasting |
| Online Access: | http://dx.doi.org/10.1155/2008/245305 |
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| Summary: | The starting point of this work is the development of a new class of partially structured LDPC codes, very well suited for hardware implementation. Specifically these codes are built so that the edges
of their parity matrix can be partitioned into two disjoint sets, namely, the structured and the random ones. For the proposed class of codes a constructive design method is provided. To assess the value of this method the constructed codes performance are presented. From these results, a novel decoding method called split decoding is introduced. Finally, to prove the effectiveness of the proposed approach a whole VLSI decoder is designed and characterized. |
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| ISSN: | 1687-7578 1687-7586 |