Optimized SM4 Hardware Implementations for Low Area Consumption
The SM4 block cipher is standardized in ISO/IEC, and it is also the national standard of commercial cryptography in China. In this paper, we propose two new techniques called “split-and-join” and “off-peak and stagger” to make SM4 more applicable to resource-constrained environments. The area optimi...
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| Format: | Article |
| Language: | English |
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Wiley
2024-01-01
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| Series: | IET Information Security |
| Online Access: | http://dx.doi.org/10.1049/2024/7047055 |
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| author | Ruolin Zhang Zejun Xiang Shasha Zhang Xiangyong Zeng Min Song |
| author_facet | Ruolin Zhang Zejun Xiang Shasha Zhang Xiangyong Zeng Min Song |
| author_sort | Ruolin Zhang |
| collection | DOAJ |
| description | The SM4 block cipher is standardized in ISO/IEC, and it is also the national standard of commercial cryptography in China. In this paper, we propose two new techniques called “split-and-join” and “off-peak and stagger” to make SM4 more applicable to resource-constrained environments. The area optimization method uses a 1-bit data path while reducing the number of registers from 64 to 8 and the number of XOR gates from 194 to 8. As a result, we report a 1-bit-serial SM4 encryption circuit that occupies 1771 GE with a latency of 2,336 cycles. Additionally, the “off-peak and stagger” technique compresses all the operations within the state update and key schedule into 32 clock cycles to reduce the latency. In other words, it takes 32 clock cycles to complete one round encryption. The new circuit occupies 1861 GE with a latency of 1,344 cycles. Moreover, we also discuss how to further reduce the latency by increasing the data path with a small area overhead to provide wider area-latency tradeoffs for SM4. Our designs make SM4 competitive with many ciphers specifically designed for lightweight cryptography. |
| format | Article |
| id | doaj-art-171155703c7c424cbd15a861d979f359 |
| institution | Kabale University |
| issn | 1751-8717 |
| language | English |
| publishDate | 2024-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | IET Information Security |
| spelling | doaj-art-171155703c7c424cbd15a861d979f3592025-02-03T07:23:40ZengWileyIET Information Security1751-87172024-01-01202410.1049/2024/7047055Optimized SM4 Hardware Implementations for Low Area ConsumptionRuolin Zhang0Zejun Xiang1Shasha Zhang2Xiangyong Zeng3Min Song4Faculty of Mathematics and StatisticsSchool of Cyber Science and TechnologySchool of Cyber Science and TechnologyFaculty of Mathematics and StatisticsSchool of MicroelectonicsThe SM4 block cipher is standardized in ISO/IEC, and it is also the national standard of commercial cryptography in China. In this paper, we propose two new techniques called “split-and-join” and “off-peak and stagger” to make SM4 more applicable to resource-constrained environments. The area optimization method uses a 1-bit data path while reducing the number of registers from 64 to 8 and the number of XOR gates from 194 to 8. As a result, we report a 1-bit-serial SM4 encryption circuit that occupies 1771 GE with a latency of 2,336 cycles. Additionally, the “off-peak and stagger” technique compresses all the operations within the state update and key schedule into 32 clock cycles to reduce the latency. In other words, it takes 32 clock cycles to complete one round encryption. The new circuit occupies 1861 GE with a latency of 1,344 cycles. Moreover, we also discuss how to further reduce the latency by increasing the data path with a small area overhead to provide wider area-latency tradeoffs for SM4. Our designs make SM4 competitive with many ciphers specifically designed for lightweight cryptography.http://dx.doi.org/10.1049/2024/7047055 |
| spellingShingle | Ruolin Zhang Zejun Xiang Shasha Zhang Xiangyong Zeng Min Song Optimized SM4 Hardware Implementations for Low Area Consumption IET Information Security |
| title | Optimized SM4 Hardware Implementations for Low Area Consumption |
| title_full | Optimized SM4 Hardware Implementations for Low Area Consumption |
| title_fullStr | Optimized SM4 Hardware Implementations for Low Area Consumption |
| title_full_unstemmed | Optimized SM4 Hardware Implementations for Low Area Consumption |
| title_short | Optimized SM4 Hardware Implementations for Low Area Consumption |
| title_sort | optimized sm4 hardware implementations for low area consumption |
| url | http://dx.doi.org/10.1049/2024/7047055 |
| work_keys_str_mv | AT ruolinzhang optimizedsm4hardwareimplementationsforlowareaconsumption AT zejunxiang optimizedsm4hardwareimplementationsforlowareaconsumption AT shashazhang optimizedsm4hardwareimplementationsforlowareaconsumption AT xiangyongzeng optimizedsm4hardwareimplementationsforlowareaconsumption AT minsong optimizedsm4hardwareimplementationsforlowareaconsumption |