An Area-Efficient Integrate-and-Fire Neuron Circuit with Enhanced Robustness against Synapse Variability in Hardware Neural Network
Neuron circuits are the fundamental building blocks in the modern neuromorphic system. Designing compact and low-power neuron circuits can significantly improve the overall area and energy efficiencies of a neuromorphic chip architecture. Here, practical neuron circuits must overcome the variations...
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| Format: | Article |
| Language: | English |
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Wiley
2023-01-01
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| Series: | IET Circuits, Devices and Systems |
| Online Access: | http://dx.doi.org/10.1049/2023/1052063 |
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| author | Arati Kumari Shah Kannan Udaya Mohanan Jisun Park Hyungsoon Shin Eou-Sik Cho Seongjae Cho |
| author_facet | Arati Kumari Shah Kannan Udaya Mohanan Jisun Park Hyungsoon Shin Eou-Sik Cho Seongjae Cho |
| author_sort | Arati Kumari Shah |
| collection | DOAJ |
| description | Neuron circuits are the fundamental building blocks in the modern neuromorphic system. Designing compact and low-power neuron circuits can significantly improve the overall area and energy efficiencies of a neuromorphic chip architecture. Here, practical neuron circuits must overcome the variations arising from nonideal behaviors of synaptic devices, such as stuck-at-fault and conductance deviation. In this study, a compact leaky integrate-and-fire neuron circuit has been designed, with resilience to synaptic device state variations, for hardware implementation of spiking neural networks (SNNs). The proposed neuron circuit is simulated on the 0.35-μm Si complementary metal-oxide-semiconductor technology node by a series of circuit simulations based on HSPICE. The proposed circuit occupies a reduced area and exhibits low power consumption (14.7 µW per spike). Furthermore, the optimized circuit design results in a high degree of tolerance toward input-current variations arising from conductance-state variations in the synapse array. Hence, the proposed neuron circuit would be capable of substantially improving the area efficiency and reliability in the realization of the hardware-oriented SNN architectures. |
| format | Article |
| id | doaj-art-170d7f7527dd4c319acacccdab3ee39e |
| institution | Kabale University |
| issn | 1751-8598 |
| language | English |
| publishDate | 2023-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | IET Circuits, Devices and Systems |
| spelling | doaj-art-170d7f7527dd4c319acacccdab3ee39e2025-02-03T01:32:00ZengWileyIET Circuits, Devices and Systems1751-85982023-01-01202310.1049/2023/1052063An Area-Efficient Integrate-and-Fire Neuron Circuit with Enhanced Robustness against Synapse Variability in Hardware Neural NetworkArati Kumari Shah0Kannan Udaya Mohanan1Jisun Park2Hyungsoon Shin3Eou-Sik Cho4Seongjae Cho5Department of Electronic EngineeringDepartment of Electronic EngineeringDepartment of Electronic and Electrical EngineeringDepartment of Electronic and Electrical EngineeringDepartment of Electronic EngineeringDepartment of Electronic and Electrical EngineeringNeuron circuits are the fundamental building blocks in the modern neuromorphic system. Designing compact and low-power neuron circuits can significantly improve the overall area and energy efficiencies of a neuromorphic chip architecture. Here, practical neuron circuits must overcome the variations arising from nonideal behaviors of synaptic devices, such as stuck-at-fault and conductance deviation. In this study, a compact leaky integrate-and-fire neuron circuit has been designed, with resilience to synaptic device state variations, for hardware implementation of spiking neural networks (SNNs). The proposed neuron circuit is simulated on the 0.35-μm Si complementary metal-oxide-semiconductor technology node by a series of circuit simulations based on HSPICE. The proposed circuit occupies a reduced area and exhibits low power consumption (14.7 µW per spike). Furthermore, the optimized circuit design results in a high degree of tolerance toward input-current variations arising from conductance-state variations in the synapse array. Hence, the proposed neuron circuit would be capable of substantially improving the area efficiency and reliability in the realization of the hardware-oriented SNN architectures.http://dx.doi.org/10.1049/2023/1052063 |
| spellingShingle | Arati Kumari Shah Kannan Udaya Mohanan Jisun Park Hyungsoon Shin Eou-Sik Cho Seongjae Cho An Area-Efficient Integrate-and-Fire Neuron Circuit with Enhanced Robustness against Synapse Variability in Hardware Neural Network IET Circuits, Devices and Systems |
| title | An Area-Efficient Integrate-and-Fire Neuron Circuit with Enhanced Robustness against Synapse Variability in Hardware Neural Network |
| title_full | An Area-Efficient Integrate-and-Fire Neuron Circuit with Enhanced Robustness against Synapse Variability in Hardware Neural Network |
| title_fullStr | An Area-Efficient Integrate-and-Fire Neuron Circuit with Enhanced Robustness against Synapse Variability in Hardware Neural Network |
| title_full_unstemmed | An Area-Efficient Integrate-and-Fire Neuron Circuit with Enhanced Robustness against Synapse Variability in Hardware Neural Network |
| title_short | An Area-Efficient Integrate-and-Fire Neuron Circuit with Enhanced Robustness against Synapse Variability in Hardware Neural Network |
| title_sort | area efficient integrate and fire neuron circuit with enhanced robustness against synapse variability in hardware neural network |
| url | http://dx.doi.org/10.1049/2023/1052063 |
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