Research on key technologies for input inrush current suppression circuit based on MOSFET Miller effect
The reliability of input inrush current suppression circuits is crucial for ensuring the stable operation of power boards, deemed one of the fundamental requirements for the safe operation of electric locomotives. In order to improve this reliability, this paper proposed a series of optimization mea...
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| Format: | Article |
| Language: | zho |
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Editorial Department of Electric Drive for Locomotives
2024-11-01
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| Series: | 机车电传动 |
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| Online Access: | http://edl.csrzic.com/thesisDetails#10.13890/j.issn.1000-128X.2024.05.102 |
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| author | LI Can LIU Yunhua LIU Guowang WU Jian WANG Fuguang ZHANG Yi |
| author_facet | LI Can LIU Yunhua LIU Guowang WU Jian WANG Fuguang ZHANG Yi |
| author_sort | LI Can |
| collection | DOAJ |
| description | The reliability of input inrush current suppression circuits is crucial for ensuring the stable operation of power boards, deemed one of the fundamental requirements for the safe operation of electric locomotives. In order to improve this reliability, this paper proposed a series of optimization measures based on the failure instance involving anti-inrush metal oxide semiconductor field effect transistors (MOSFET) in a power supply application. The initial analysis addressed the waveform timing of MOSFETs using a simplified model, deriving the working principles and related calculation formulas for input inrush current suppression circuits. Subsequently, a loss evaluation method for the MOSFETs’ safe operation area (SOA) was introduced, based on the Miller effect. Through evaluating SOA loss in the measured waveform, the root cause of the anti-inrush MOSFET failure was identified to be the insufficient power derating of the device at elevated temperatures. To address this issue, optimization measures were proposed, such as adjusting the device model according to failure cause, extending the Miller platform time, and implementing a delayed start-up. The results from model simulations were harnessed to calculate energy demands for switching on the anti-inrush MOSFET and energy bearing limits under various input conditions. The calculation results show that the MOSFET power derating after optimization aligned with requirements throughout the entire input voltage and temperature ranges. The subsequent experiments were conducted on an engineering prototype under full conditions. The experimental results demonstrated the efficacy of the proposed optimization measures in effectively enhancing the reliability of input inrush current suppression circuits. |
| format | Article |
| id | doaj-art-16bfc26f00894864bb6c9cd13d9c71a9 |
| institution | DOAJ |
| issn | 1000-128X |
| language | zho |
| publishDate | 2024-11-01 |
| publisher | Editorial Department of Electric Drive for Locomotives |
| record_format | Article |
| series | 机车电传动 |
| spelling | doaj-art-16bfc26f00894864bb6c9cd13d9c71a92025-08-20T03:09:25ZzhoEditorial Department of Electric Drive for Locomotives机车电传动1000-128X2024-11-0110411182049022Research on key technologies for input inrush current suppression circuit based on MOSFET Miller effectLI CanLIU YunhuaLIU GuowangWU JianWANG FuguangZHANG YiThe reliability of input inrush current suppression circuits is crucial for ensuring the stable operation of power boards, deemed one of the fundamental requirements for the safe operation of electric locomotives. In order to improve this reliability, this paper proposed a series of optimization measures based on the failure instance involving anti-inrush metal oxide semiconductor field effect transistors (MOSFET) in a power supply application. The initial analysis addressed the waveform timing of MOSFETs using a simplified model, deriving the working principles and related calculation formulas for input inrush current suppression circuits. Subsequently, a loss evaluation method for the MOSFETs’ safe operation area (SOA) was introduced, based on the Miller effect. Through evaluating SOA loss in the measured waveform, the root cause of the anti-inrush MOSFET failure was identified to be the insufficient power derating of the device at elevated temperatures. To address this issue, optimization measures were proposed, such as adjusting the device model according to failure cause, extending the Miller platform time, and implementing a delayed start-up. The results from model simulations were harnessed to calculate energy demands for switching on the anti-inrush MOSFET and energy bearing limits under various input conditions. The calculation results show that the MOSFET power derating after optimization aligned with requirements throughout the entire input voltage and temperature ranges. The subsequent experiments were conducted on an engineering prototype under full conditions. The experimental results demonstrated the efficacy of the proposed optimization measures in effectively enhancing the reliability of input inrush current suppression circuits.http://edl.csrzic.com/thesisDetails#10.13890/j.issn.1000-128X.2024.05.102anti-inrush MOSFETMiller platformsafe operation area (SOA)device derating |
| spellingShingle | LI Can LIU Yunhua LIU Guowang WU Jian WANG Fuguang ZHANG Yi Research on key technologies for input inrush current suppression circuit based on MOSFET Miller effect 机车电传动 anti-inrush MOSFET Miller platform safe operation area (SOA) device derating |
| title | Research on key technologies for input inrush current suppression circuit based on MOSFET Miller effect |
| title_full | Research on key technologies for input inrush current suppression circuit based on MOSFET Miller effect |
| title_fullStr | Research on key technologies for input inrush current suppression circuit based on MOSFET Miller effect |
| title_full_unstemmed | Research on key technologies for input inrush current suppression circuit based on MOSFET Miller effect |
| title_short | Research on key technologies for input inrush current suppression circuit based on MOSFET Miller effect |
| title_sort | research on key technologies for input inrush current suppression circuit based on mosfet miller effect |
| topic | anti-inrush MOSFET Miller platform safe operation area (SOA) device derating |
| url | http://edl.csrzic.com/thesisDetails#10.13890/j.issn.1000-128X.2024.05.102 |
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