New Multiply-Accumulate Circuits Based on Variable Latency Speculative Architectures with Asynchronous Data Paths
In this paper, variable latency speculative Multiply-Accumulator (MAC) architectures are introduced. The proposed architectures use the idea of integrating the results vectors of multiplier in parallel with the accumulator to create asynchronous data paths design. The proposed variable latency specu...
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| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
OICC Press
2022-06-01
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| Series: | Majlesi Journal of Electrical Engineering |
| Subjects: | |
| Online Access: | https://oiccpress.com/mjee/article/view/4950 |
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| Summary: | In this paper, variable latency speculative Multiply-Accumulator (MAC) architectures are introduced. The proposed architectures use the idea of integrating the results vectors of multiplier in parallel with the accumulator to create asynchronous data paths design. The proposed variable latency speculative MACs consist of two short and long data paths and a circuit is used to select a suitable path with minimum overhead. In order to investigate variable latency speculative MACs performances, proposed architectures have been synthesized using the Faradayâs 90 nm technology library, for operand lengths 8, 16 and 32 bits. Obtained results show that the proposed MAC architectures provide a variety of trade-offs in the power-delay-area space that outperform the existing designs that use only the integration technique. |
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| ISSN: | 2345-377X 2345-3796 |