FPGA implementation of normalized correlation function
Correlation analysis is a frequently used tool in signal detection and classification tasks. This paper presents the design and FPGA implementations of a hardware module for calculating the Pearson correlation coefficient. This module is designed for use in signal template matching, where a measurem...
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| Format: | Article |
| Language: | English |
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Polish Academy of Sciences
2025-07-01
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| Series: | International Journal of Electronics and Telecommunications |
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| Online Access: | https://journals.pan.pl/Content/135748/20-5147-Mroczek-sk.pdf |
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| _version_ | 1849470209809711104 |
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| author | Krzysztof Mroczek |
| author_facet | Krzysztof Mroczek |
| author_sort | Krzysztof Mroczek |
| collection | DOAJ |
| description | Correlation analysis is a frequently used tool in signal detection and classification tasks. This paper presents the design and FPGA implementations of a hardware module for calculating the Pearson correlation coefficient. This module is designed for use in signal template matching, where a measurement signal is correlated with a template. It has been described in Verilog and implemented on Intel Cyclone V FPGA. The module consists of two main parts, which are: a correlation filter and normalization modules. Correlation filters performing the calculation in the time domain and in the frequency domain are described. The project has been verified in simulation using ModelSim and checked on hardware. As a result of this work, hardware IP cores are developed enabling parametrization and programming in data word-lengths, filter size, calculation speed, FFT/IFFT size, length, and number of processing templates. Developed resources are intended to be used in FPGA-based hardware, e.g. DAQ systems, working with sampling frequencies from kHz to above 130 MHz. |
| format | Article |
| id | doaj-art-13d79d1846dc4621ae079157b80e12b9 |
| institution | Kabale University |
| issn | 2081-8491 2300-1933 |
| language | English |
| publishDate | 2025-07-01 |
| publisher | Polish Academy of Sciences |
| record_format | Article |
| series | International Journal of Electronics and Telecommunications |
| spelling | doaj-art-13d79d1846dc4621ae079157b80e12b92025-08-20T03:25:12ZengPolish Academy of SciencesInternational Journal of Electronics and Telecommunications2081-84912300-19332025-07-01vol. 71No 318https://doi.org/10.24425/ijet.2025.153627FPGA implementation of normalized correlation functionKrzysztof Mroczek0Institute of Radioelectronics and Multimedia Technology (IRTM), Warsaw University of Technology, PolandCorrelation analysis is a frequently used tool in signal detection and classification tasks. This paper presents the design and FPGA implementations of a hardware module for calculating the Pearson correlation coefficient. This module is designed for use in signal template matching, where a measurement signal is correlated with a template. It has been described in Verilog and implemented on Intel Cyclone V FPGA. The module consists of two main parts, which are: a correlation filter and normalization modules. Correlation filters performing the calculation in the time domain and in the frequency domain are described. The project has been verified in simulation using ModelSim and checked on hardware. As a result of this work, hardware IP cores are developed enabling parametrization and programming in data word-lengths, filter size, calculation speed, FFT/IFFT size, length, and number of processing templates. Developed resources are intended to be used in FPGA-based hardware, e.g. DAQ systems, working with sampling frequencies from kHz to above 130 MHz.https://journals.pan.pl/Content/135748/20-5147-Mroczek-sk.pdfcorrelationhardware algorithmsfpgaembedded systemstime series analysispulse recognition |
| spellingShingle | Krzysztof Mroczek FPGA implementation of normalized correlation function International Journal of Electronics and Telecommunications correlation hardware algorithms fpga embedded systems time series analysis pulse recognition |
| title | FPGA implementation of normalized correlation function |
| title_full | FPGA implementation of normalized correlation function |
| title_fullStr | FPGA implementation of normalized correlation function |
| title_full_unstemmed | FPGA implementation of normalized correlation function |
| title_short | FPGA implementation of normalized correlation function |
| title_sort | fpga implementation of normalized correlation function |
| topic | correlation hardware algorithms fpga embedded systems time series analysis pulse recognition |
| url | https://journals.pan.pl/Content/135748/20-5147-Mroczek-sk.pdf |
| work_keys_str_mv | AT krzysztofmroczek fpgaimplementationofnormalizedcorrelationfunction |