Energy efficient design and implementation of approximate adder for image processing applications
Approximate computing is a new technique that promises to speed up computations while preserving a level of precision suitable for error-tolerant systems such as neural networks and graphics. At the edge, a lot of computationally complex methods are now in use. As such, designing quick a...
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| Format: | Article |
| Language: | English |
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Faculty of Technical Sciences in Cacak
2025-01-01
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| Series: | Serbian Journal of Electrical Engineering |
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| Online Access: | https://doiserbia.nb.rs/img/doi/1451-4869/2025/1451-48692501075N.pdf |
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| author | Naik Jatothu Brahmaiah Kumar Kanagala Sateesh Krishnaiah Kondragunta Rama Koteswararao Seelam |
| author_facet | Naik Jatothu Brahmaiah Kumar Kanagala Sateesh Krishnaiah Kondragunta Rama Koteswararao Seelam |
| author_sort | Naik Jatothu Brahmaiah |
| collection | DOAJ |
| description | Approximate computing is a new technique that promises to speed up
computations while preserving a level of precision suitable for
error-tolerant systems such as neural networks and graphics. At the edge, a
lot of computationally complex methods are now in use. As such, designing
quick and low-energy circuits is crucial. This work presents a novel
approximate full adder approach that lowers power consumption and delay at
the expense of some output mistakes. To achieve these objectives, the
proposed full adder architecture makes use of fundamental gate logic
reduction techniques. Evaluations based on the Intel FPGA synthesis tool
indicate that the suggested adder surpasses state-of-the-art techniques in
terms of power, speed, and propagation delay. The design parameters - area,
power dissipation, and latent characteristics of proposed adder are verified
by simulation using EDA tools. The results demonstrate that our proposed
approximate adder runs faster and requires fewer logic components than
earlier equivalent systems. The synthesis reports testify to the fact that
compared to other adders currently in use, the suggested adder used less
logic elements. Furthermore, suggested approximation adders were used to
execute image additions. Using image addition, the image quantitative
statistics are used to application-level accuracy metrics analysis.
Quantitative results confirm the superior functioning of the full adder cell
approximation over comparable models. |
| format | Article |
| id | doaj-art-13c6a9392a8f4aa3a97e5fa80fdb5df0 |
| institution | OA Journals |
| issn | 1451-4869 2217-7183 |
| language | English |
| publishDate | 2025-01-01 |
| publisher | Faculty of Technical Sciences in Cacak |
| record_format | Article |
| series | Serbian Journal of Electrical Engineering |
| spelling | doaj-art-13c6a9392a8f4aa3a97e5fa80fdb5df02025-08-20T02:29:56ZengFaculty of Technical Sciences in CacakSerbian Journal of Electrical Engineering1451-48692217-71832025-01-01221759210.2298/SJEE2501075B1451-48692501075NEnergy efficient design and implementation of approximate adder for image processing applicationsNaik Jatothu Brahmaiah0https://orcid.org/0000-0002-9333-9235Kumar Kanagala Sateesh1https://orcid.org/0000-0001-6233-7790Krishnaiah Kondragunta Rama2https://orcid.org/0000-0002-9069-766XKoteswararao Seelam3https://orcid.org/0000-0002-3337-0361Department of Electronics and Communication Engineering, Narasaraopeta Engineering College, Andhra Pradesh, IndiaDepartment of Electronics and Communication Engineering, Sreenidhi Institute of Science and Technology, Telangana, IndiaDepartment of Computer Science and Engineering, R.K.College of Engineering, Andhra Pradesh, IndiaDepartment of Electronics and Communication Engineering, Lingayas Institute of Management and Technology, Andhra Pradesh, IndiaApproximate computing is a new technique that promises to speed up computations while preserving a level of precision suitable for error-tolerant systems such as neural networks and graphics. At the edge, a lot of computationally complex methods are now in use. As such, designing quick and low-energy circuits is crucial. This work presents a novel approximate full adder approach that lowers power consumption and delay at the expense of some output mistakes. To achieve these objectives, the proposed full adder architecture makes use of fundamental gate logic reduction techniques. Evaluations based on the Intel FPGA synthesis tool indicate that the suggested adder surpasses state-of-the-art techniques in terms of power, speed, and propagation delay. The design parameters - area, power dissipation, and latent characteristics of proposed adder are verified by simulation using EDA tools. The results demonstrate that our proposed approximate adder runs faster and requires fewer logic components than earlier equivalent systems. The synthesis reports testify to the fact that compared to other adders currently in use, the suggested adder used less logic elements. Furthermore, suggested approximation adders were used to execute image additions. Using image addition, the image quantitative statistics are used to application-level accuracy metrics analysis. Quantitative results confirm the superior functioning of the full adder cell approximation over comparable models.https://doiserbia.nb.rs/img/doi/1451-4869/2025/1451-48692501075N.pdffpgaimage processingadder designimage additionapproximate computing |
| spellingShingle | Naik Jatothu Brahmaiah Kumar Kanagala Sateesh Krishnaiah Kondragunta Rama Koteswararao Seelam Energy efficient design and implementation of approximate adder for image processing applications Serbian Journal of Electrical Engineering fpga image processing adder design image addition approximate computing |
| title | Energy efficient design and implementation of approximate adder for image processing applications |
| title_full | Energy efficient design and implementation of approximate adder for image processing applications |
| title_fullStr | Energy efficient design and implementation of approximate adder for image processing applications |
| title_full_unstemmed | Energy efficient design and implementation of approximate adder for image processing applications |
| title_short | Energy efficient design and implementation of approximate adder for image processing applications |
| title_sort | energy efficient design and implementation of approximate adder for image processing applications |
| topic | fpga image processing adder design image addition approximate computing |
| url | https://doiserbia.nb.rs/img/doi/1451-4869/2025/1451-48692501075N.pdf |
| work_keys_str_mv | AT naikjatothubrahmaiah energyefficientdesignandimplementationofapproximateadderforimageprocessingapplications AT kumarkanagalasateesh energyefficientdesignandimplementationofapproximateadderforimageprocessingapplications AT krishnaiahkondraguntarama energyefficientdesignandimplementationofapproximateadderforimageprocessingapplications AT koteswararaoseelam energyefficientdesignandimplementationofapproximateadderforimageprocessingapplications |