Z Packed U-Cell Modular Multilevel Converter for STATCOM Applications
The Modular Multilevel Converter (MMC) is a promising topology for STATCOM applications due to its key features, such as modularity, scalability, and reduced harmonic content. Increasing the number of voltage levels in MMC reduces harmonics but simultaneously increases the number of submodules (SMs)...
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IEEE
2025-01-01
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| Series: | IEEE Access |
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| Online Access: | https://ieeexplore.ieee.org/document/10981426/ |
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| author | Sandy Atanalian Fadia Sebaaly Rawad Zgheib Kamal Al-Haddad |
| author_facet | Sandy Atanalian Fadia Sebaaly Rawad Zgheib Kamal Al-Haddad |
| author_sort | Sandy Atanalian |
| collection | DOAJ |
| description | The Modular Multilevel Converter (MMC) is a promising topology for STATCOM applications due to its key features, such as modularity, scalability, and reduced harmonic content. Increasing the number of voltage levels in MMC reduces harmonics but simultaneously increases the number of submodules (SMs) per arm, leading to larger sizes and higher costs, which presents a challenge. To address this, this article introduces a novel 17-level MMC-STATCOM based on the Z Packed U-Cell (ZPUC) converter as its SM, which enables the generation of more voltage levels with fewer components and reduced harmonic content, offering significant advantages in terms of size and cost. Given the complex structure of the proposed converter and the associated challenges in building a physical prototype, real-time (RT) simulation using FPGA technology is employed for validation. The key contributions include integrating the ZPUC-SM into a three-phase STATCOM for the first time and adapting the converter model and its control system to RT tools, including RT-LAB with an electric hardware solver for FPGA execution. In addition, capacitor voltage balancing and energy sorting algorithms are integrated within Phase-Shift Pulse Width Modulation, eliminating the need for an additional controller while maintaining the floating capacitors of ZPUC-SMs balanced and regulated. The specifications of the proposed converter are defined, the mathematical model and control system are derived, and a real-time implementation based on CPU and FPGA execution is built to verify the scheme. The obtained RT simulation results provide practical evidence confirming the effective operation of the proposed scheme in VAR compensation mode. |
| format | Article |
| id | doaj-art-10b16fb338b34abeb834aa625f2e6555 |
| institution | OA Journals |
| issn | 2169-3536 |
| language | English |
| publishDate | 2025-01-01 |
| publisher | IEEE |
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| spelling | doaj-art-10b16fb338b34abeb834aa625f2e65552025-08-20T02:28:15ZengIEEEIEEE Access2169-35362025-01-0113787957880710.1109/ACCESS.2025.356601510981426Z Packed U-Cell Modular Multilevel Converter for STATCOM ApplicationsSandy Atanalian0https://orcid.org/0000-0002-3442-0818Fadia Sebaaly1https://orcid.org/0000-0003-0932-9526Rawad Zgheib2https://orcid.org/0000-0001-9148-0473Kamal Al-Haddad3https://orcid.org/0000-0003-0276-4277Groupe de Recherche en Électronique de Puissance et Commandes Industrielles, École de Technologie Supérieure, Montreal, QC, CanadaCentre de Recherche d’Hydro-Québec (IREQ), Hydro-Québec, Varennes, QC, CanadaG&W Electric Company, Bolingbrook, IL, USAGroupe de Recherche en Électronique de Puissance et Commandes Industrielles, École de Technologie Supérieure, Montreal, QC, CanadaThe Modular Multilevel Converter (MMC) is a promising topology for STATCOM applications due to its key features, such as modularity, scalability, and reduced harmonic content. Increasing the number of voltage levels in MMC reduces harmonics but simultaneously increases the number of submodules (SMs) per arm, leading to larger sizes and higher costs, which presents a challenge. To address this, this article introduces a novel 17-level MMC-STATCOM based on the Z Packed U-Cell (ZPUC) converter as its SM, which enables the generation of more voltage levels with fewer components and reduced harmonic content, offering significant advantages in terms of size and cost. Given the complex structure of the proposed converter and the associated challenges in building a physical prototype, real-time (RT) simulation using FPGA technology is employed for validation. The key contributions include integrating the ZPUC-SM into a three-phase STATCOM for the first time and adapting the converter model and its control system to RT tools, including RT-LAB with an electric hardware solver for FPGA execution. In addition, capacitor voltage balancing and energy sorting algorithms are integrated within Phase-Shift Pulse Width Modulation, eliminating the need for an additional controller while maintaining the floating capacitors of ZPUC-SMs balanced and regulated. The specifications of the proposed converter are defined, the mathematical model and control system are derived, and a real-time implementation based on CPU and FPGA execution is built to verify the scheme. The obtained RT simulation results provide practical evidence confirming the effective operation of the proposed scheme in VAR compensation mode.https://ieeexplore.ieee.org/document/10981426/Electric hardware solvermodular multilevel converterreal-time implementationRT-LABSTATCOMsubmodule |
| spellingShingle | Sandy Atanalian Fadia Sebaaly Rawad Zgheib Kamal Al-Haddad Z Packed U-Cell Modular Multilevel Converter for STATCOM Applications IEEE Access Electric hardware solver modular multilevel converter real-time implementation RT-LAB STATCOM submodule |
| title | Z Packed U-Cell Modular Multilevel Converter for STATCOM Applications |
| title_full | Z Packed U-Cell Modular Multilevel Converter for STATCOM Applications |
| title_fullStr | Z Packed U-Cell Modular Multilevel Converter for STATCOM Applications |
| title_full_unstemmed | Z Packed U-Cell Modular Multilevel Converter for STATCOM Applications |
| title_short | Z Packed U-Cell Modular Multilevel Converter for STATCOM Applications |
| title_sort | z packed u cell modular multilevel converter for statcom applications |
| topic | Electric hardware solver modular multilevel converter real-time implementation RT-LAB STATCOM submodule |
| url | https://ieeexplore.ieee.org/document/10981426/ |
| work_keys_str_mv | AT sandyatanalian zpackeducellmodularmultilevelconverterforstatcomapplications AT fadiasebaaly zpackeducellmodularmultilevelconverterforstatcomapplications AT rawadzgheib zpackeducellmodularmultilevelconverterforstatcomapplications AT kamalalhaddad zpackeducellmodularmultilevelconverterforstatcomapplications |