A Novel Multilevel Inverter Topology Generating a 19-Level Output Regulated by the PD-PWM Method
Traditional multilevel inverter topologies, such FC, NPC, and CHB, have a few significant disadvantages. They need a great number of parts, which raises the complexity, expense, and switching losses. Furthermore, their intricate control schemes make voltage balancing and synchronization challenging....
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MDPI AG
2025-06-01
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| Series: | Energies |
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| Online Access: | https://www.mdpi.com/1996-1073/18/13/3227 |
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| author | Sofia Lemssaddak Abdelhafid Ait Elmahjoub Mohamed Tabaa Adnane El-Alami Mourad Zegrari |
| author_facet | Sofia Lemssaddak Abdelhafid Ait Elmahjoub Mohamed Tabaa Adnane El-Alami Mourad Zegrari |
| author_sort | Sofia Lemssaddak |
| collection | DOAJ |
| description | Traditional multilevel inverter topologies, such FC, NPC, and CHB, have a few significant disadvantages. They need a great number of parts, which raises the complexity, expense, and switching losses. Furthermore, their intricate control schemes make voltage balancing and synchronization challenging. Lastly, under some circumstances, they experience severe harmonic distortion, necessitating the inclusion of expensive filters to enhance signal quality. This paper proposes a novel multilevel converter topology that uses the phase-disposition PWM (PD-PWM) technique to control a 19-level output. This new configuration maintains performance comparable to the CHB-MLI reference while using fewer switches, simplifying control, and reducing costs. Our approach is based on extensive simulations conducted in the MATLAB Simulink environment, with results compared to the CHB-MLI. A low-pass filter is added to improve the output voltage quality, reducing the THD% to 1.33%. This strategy offers several advantages, including simpler control, lower costs, increased reliability, and higher-quality output. The system was replicated using MATLAB Simulink and validated through hardware-in-the-loop (HIL) testing. The HIL method ensures real-world testing without causing damage to the hardware. The integrated system includes sensors and necessary hardware for a comprehensive energy management solution. |
| format | Article |
| id | doaj-art-0dd0316615384b069d7d537d35c827bb |
| institution | Kabale University |
| issn | 1996-1073 |
| language | English |
| publishDate | 2025-06-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Energies |
| spelling | doaj-art-0dd0316615384b069d7d537d35c827bb2025-08-20T03:28:33ZengMDPI AGEnergies1996-10732025-06-011813322710.3390/en18133227A Novel Multilevel Inverter Topology Generating a 19-Level Output Regulated by the PD-PWM MethodSofia Lemssaddak0Abdelhafid Ait Elmahjoub1Mohamed Tabaa2Adnane El-Alami3Mourad Zegrari4Digital Engineering for Leading Technology and Automation Laboratory (DELTA Lab), ENSAM Casablanca, Hassan II University of Casablanca, Casablanca 20360, MoroccoDigital Engineering for Leading Technology and Automation Laboratory (DELTA Lab), ENSAM Casablanca, Hassan II University of Casablanca, Casablanca 20360, MoroccoMultidisciplinary Laboratory of Research and Innovation (LPRI), Moroccan School of Engineering Sciences (EMSI), Casablanca 20250, MoroccoDigital Engineering for Leading Technology and Automation Laboratory (DELTA Lab), ENSAM Casablanca, Hassan II University of Casablanca, Casablanca 20360, MoroccoDigital Engineering for Leading Technology and Automation Laboratory (DELTA Lab), ENSAM Casablanca, Hassan II University of Casablanca, Casablanca 20360, MoroccoTraditional multilevel inverter topologies, such FC, NPC, and CHB, have a few significant disadvantages. They need a great number of parts, which raises the complexity, expense, and switching losses. Furthermore, their intricate control schemes make voltage balancing and synchronization challenging. Lastly, under some circumstances, they experience severe harmonic distortion, necessitating the inclusion of expensive filters to enhance signal quality. This paper proposes a novel multilevel converter topology that uses the phase-disposition PWM (PD-PWM) technique to control a 19-level output. This new configuration maintains performance comparable to the CHB-MLI reference while using fewer switches, simplifying control, and reducing costs. Our approach is based on extensive simulations conducted in the MATLAB Simulink environment, with results compared to the CHB-MLI. A low-pass filter is added to improve the output voltage quality, reducing the THD% to 1.33%. This strategy offers several advantages, including simpler control, lower costs, increased reliability, and higher-quality output. The system was replicated using MATLAB Simulink and validated through hardware-in-the-loop (HIL) testing. The HIL method ensures real-world testing without causing damage to the hardware. The integrated system includes sensors and necessary hardware for a comprehensive energy management solution.https://www.mdpi.com/1996-1073/18/13/3227PD-PWM: phase-disposition pulse width modulationCHB-MLI: cascaded H-bridge multilevel inverterTHD: total harmonic distortionhardware in the loop |
| spellingShingle | Sofia Lemssaddak Abdelhafid Ait Elmahjoub Mohamed Tabaa Adnane El-Alami Mourad Zegrari A Novel Multilevel Inverter Topology Generating a 19-Level Output Regulated by the PD-PWM Method Energies PD-PWM: phase-disposition pulse width modulation CHB-MLI: cascaded H-bridge multilevel inverter THD: total harmonic distortion hardware in the loop |
| title | A Novel Multilevel Inverter Topology Generating a 19-Level Output Regulated by the PD-PWM Method |
| title_full | A Novel Multilevel Inverter Topology Generating a 19-Level Output Regulated by the PD-PWM Method |
| title_fullStr | A Novel Multilevel Inverter Topology Generating a 19-Level Output Regulated by the PD-PWM Method |
| title_full_unstemmed | A Novel Multilevel Inverter Topology Generating a 19-Level Output Regulated by the PD-PWM Method |
| title_short | A Novel Multilevel Inverter Topology Generating a 19-Level Output Regulated by the PD-PWM Method |
| title_sort | novel multilevel inverter topology generating a 19 level output regulated by the pd pwm method |
| topic | PD-PWM: phase-disposition pulse width modulation CHB-MLI: cascaded H-bridge multilevel inverter THD: total harmonic distortion hardware in the loop |
| url | https://www.mdpi.com/1996-1073/18/13/3227 |
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