DPFFs: C2MOS Direct Path Flip-Flops for Process-Resilient Ultradynamic Voltage Scaling
We propose two master-slave flip-flops (FFs) that utilize the clocked CMOS (C2MOS) technique with an internal direct connection along the main signal propagation path between the master and slave latches and adopt an adaptive body bias technique to improve circuit robustness. C2MOS structure improve...
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| Format: | Article |
| Language: | English |
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Wiley
2016-01-01
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| Series: | Journal of Electrical and Computer Engineering |
| Online Access: | http://dx.doi.org/10.1155/2016/8268917 |
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| author | Myeong-Eun Hwang Sungoh Kwon |
| author_facet | Myeong-Eun Hwang Sungoh Kwon |
| author_sort | Myeong-Eun Hwang |
| collection | DOAJ |
| description | We propose two master-slave flip-flops (FFs) that utilize the clocked CMOS (C2MOS) technique with an internal direct connection along the main signal propagation path between the master and slave latches and adopt an adaptive body bias technique to improve circuit robustness. C2MOS structure improves the setup margin and robustness while providing full compatibility with the standard cell characterization flow. Further, the direct path shortens the logic depth and thus speeds up signal propagation, which can be optimized for less power and smaller area. Measurements from test circuits fabricated in 130 nm technology show that the proposed FF operates down to 60 mV, consuming 24.7 pW while improving the propagation delay, dynamic power, and leakage by 22%, 9%, and 13%, respectively, compared with conventional FFs at the iso-output-load condition. The proposed FFs are integrated into an 8×8 FIR filter which successfully operates all the way down to 85 mV. |
| format | Article |
| id | doaj-art-070b2fb6ee3845a68f09d067e4a92cf5 |
| institution | Kabale University |
| issn | 2090-0147 2090-0155 |
| language | English |
| publishDate | 2016-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | Journal of Electrical and Computer Engineering |
| spelling | doaj-art-070b2fb6ee3845a68f09d067e4a92cf52025-08-20T03:55:24ZengWileyJournal of Electrical and Computer Engineering2090-01472090-01552016-01-01201610.1155/2016/82689178268917DPFFs: C2MOS Direct Path Flip-Flops for Process-Resilient Ultradynamic Voltage ScalingMyeong-Eun Hwang0Sungoh Kwon1Memory Division, Samsung Electronics Inc., Hwaseong, Gyeonggi 18448, Republic of KoreaSchool of Electrical Engineering, University of Ulsan, Nam-gu, Ulsan 44610, Republic of KoreaWe propose two master-slave flip-flops (FFs) that utilize the clocked CMOS (C2MOS) technique with an internal direct connection along the main signal propagation path between the master and slave latches and adopt an adaptive body bias technique to improve circuit robustness. C2MOS structure improves the setup margin and robustness while providing full compatibility with the standard cell characterization flow. Further, the direct path shortens the logic depth and thus speeds up signal propagation, which can be optimized for less power and smaller area. Measurements from test circuits fabricated in 130 nm technology show that the proposed FF operates down to 60 mV, consuming 24.7 pW while improving the propagation delay, dynamic power, and leakage by 22%, 9%, and 13%, respectively, compared with conventional FFs at the iso-output-load condition. The proposed FFs are integrated into an 8×8 FIR filter which successfully operates all the way down to 85 mV.http://dx.doi.org/10.1155/2016/8268917 |
| spellingShingle | Myeong-Eun Hwang Sungoh Kwon DPFFs: C2MOS Direct Path Flip-Flops for Process-Resilient Ultradynamic Voltage Scaling Journal of Electrical and Computer Engineering |
| title | DPFFs: C2MOS Direct Path Flip-Flops for Process-Resilient Ultradynamic Voltage Scaling |
| title_full | DPFFs: C2MOS Direct Path Flip-Flops for Process-Resilient Ultradynamic Voltage Scaling |
| title_fullStr | DPFFs: C2MOS Direct Path Flip-Flops for Process-Resilient Ultradynamic Voltage Scaling |
| title_full_unstemmed | DPFFs: C2MOS Direct Path Flip-Flops for Process-Resilient Ultradynamic Voltage Scaling |
| title_short | DPFFs: C2MOS Direct Path Flip-Flops for Process-Resilient Ultradynamic Voltage Scaling |
| title_sort | dpffs c2mos direct path flip flops for process resilient ultradynamic voltage scaling |
| url | http://dx.doi.org/10.1155/2016/8268917 |
| work_keys_str_mv | AT myeongeunhwang dpffsc2mosdirectpathflipflopsforprocessresilientultradynamicvoltagescaling AT sungohkwon dpffsc2mosdirectpathflipflopsforprocessresilientultradynamicvoltagescaling |