Comparative analysis of adders hardware implementation on FPGA
In this work we considered two types of adders for addition of two binary numbers implementation: carry propagate adders and parallel-prefix adders. In this article simulation on FPGA for both architectures and their comparative analysis is made. Simulation results for 4, 8, 16 and 32-bits circuits...
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| Format: | Article |
| Language: | Russian |
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North-Caucasus Federal University
2022-09-01
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| Series: | Наука. Инновации. Технологии |
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| Online Access: | https://scienceit.elpub.ru/jour/article/view/300 |
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| author | Nikolay Ivanovich Chervyakov Pavel Alekseyevich Lyakhov Maria Vasilevna Valueva O. V. Krivolapova |
| author_facet | Nikolay Ivanovich Chervyakov Pavel Alekseyevich Lyakhov Maria Vasilevna Valueva O. V. Krivolapova |
| author_sort | Nikolay Ivanovich Chervyakov |
| collection | DOAJ |
| description | In this work we considered two types of adders for addition of two binary numbers implementation: carry propagate adders and parallel-prefix adders. In this article simulation on FPGA for both architectures and their comparative analysis is made. Simulation results for 4, 8, 16 and 32-bits circuits showed that parallel-prefix architecture using gives the gain in speed up to 41% compared to sequential architecture through increasing the hardware costs up to 71%. Parallel-prefix adders should use the for those applications, in which the maximization of speed is the main objective. On the other hand, carry propagate adder is better for hardware costs and power consumption decrease. |
| format | Article |
| id | doaj-art-060a272e2cd349d3a2e44a8e10fa6623 |
| institution | Kabale University |
| issn | 2308-4758 |
| language | Russian |
| publishDate | 2022-09-01 |
| publisher | North-Caucasus Federal University |
| record_format | Article |
| series | Наука. Инновации. Технологии |
| spelling | doaj-art-060a272e2cd349d3a2e44a8e10fa66232025-08-20T03:42:25ZrusNorth-Caucasus Federal UniversityНаука. Инновации. Технологии2308-47582022-09-010499108299Comparative analysis of adders hardware implementation on FPGANikolay Ivanovich Chervyakov0Pavel Alekseyevich Lyakhov1Maria Vasilevna Valueva2O. V. Krivolapova3North Caucasus Federal UniversityNorth Caucasus Federal UniversityNorth Caucasus Federal UniversityNorth Caucasus Federal UniversityIn this work we considered two types of adders for addition of two binary numbers implementation: carry propagate adders and parallel-prefix adders. In this article simulation on FPGA for both architectures and their comparative analysis is made. Simulation results for 4, 8, 16 and 32-bits circuits showed that parallel-prefix architecture using gives the gain in speed up to 41% compared to sequential architecture through increasing the hardware costs up to 71%. Parallel-prefix adders should use the for those applications, in which the maximization of speed is the main objective. On the other hand, carry propagate adder is better for hardware costs and power consumption decrease.https://scienceit.elpub.ru/jour/article/view/300цифровое устройствосумматор с последовательным переносомпараллельно-префиксный сумматорdigital circuitcarry propagate adderparallel-prefix adder |
| spellingShingle | Nikolay Ivanovich Chervyakov Pavel Alekseyevich Lyakhov Maria Vasilevna Valueva O. V. Krivolapova Comparative analysis of adders hardware implementation on FPGA Наука. Инновации. Технологии цифровое устройство сумматор с последовательным переносом параллельно-префиксный сумматор digital circuit carry propagate adder parallel-prefix adder |
| title | Comparative analysis of adders hardware implementation on FPGA |
| title_full | Comparative analysis of adders hardware implementation on FPGA |
| title_fullStr | Comparative analysis of adders hardware implementation on FPGA |
| title_full_unstemmed | Comparative analysis of adders hardware implementation on FPGA |
| title_short | Comparative analysis of adders hardware implementation on FPGA |
| title_sort | comparative analysis of adders hardware implementation on fpga |
| topic | цифровое устройство сумматор с последовательным переносом параллельно-префиксный сумматор digital circuit carry propagate adder parallel-prefix adder |
| url | https://scienceit.elpub.ru/jour/article/view/300 |
| work_keys_str_mv | AT nikolayivanovichchervyakov comparativeanalysisofaddershardwareimplementationonfpga AT pavelalekseyevichlyakhov comparativeanalysisofaddershardwareimplementationonfpga AT mariavasilevnavalueva comparativeanalysisofaddershardwareimplementationonfpga AT ovkrivolapova comparativeanalysisofaddershardwareimplementationonfpga |