Hybrid Cat-Transmon Architecture for Scalable, Hardware-Efficient Quantum Error Correction
Dissipative cat qubits are a promising physical platform for quantum computing, since their large noise bias can enable more hardware-efficient quantum error correction. In this work we theoretically study the long-term prospects of a hybrid cat-transmon quantum computing architecture where dissipat...
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| Main Authors: | , , , , , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
American Physical Society
2025-07-01
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| Series: | PRX Quantum |
| Online Access: | http://doi.org/10.1103/75x7-5ysv |
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| Summary: | Dissipative cat qubits are a promising physical platform for quantum computing, since their large noise bias can enable more hardware-efficient quantum error correction. In this work we theoretically study the long-term prospects of a hybrid cat-transmon quantum computing architecture where dissipative cat qubits play the role of data qubits, and error syndromes are measured using ancillary transmon qubits. The cat qubits’ noise bias enables more hardware-efficient quantum error correction, and the use of transmons allows for practical, high-fidelity syndrome measurement. While correction of the dominant cat Z errors with a repetition code has recently been demonstrated in experiment, here we show how the architecture can be scaled beyond a repetition code. In particular, we propose a cat-transmon entangling gate that enables the correction of residual cat X errors in a thin rectangular surface code, so that logical error can be arbitrarily suppressed by increasing code distance. We numerically estimate logical memory performance, finding significant overhead reductions in comparison to architectures without biased noise. For example, with current state-of-the-art coherence, physical error rates of 10^{−3} and noise biases in the range 10^{3}–10^{4} are achievable. With this level of performance, the qubit overhead required to reach algorithmically relevant logical error rates with the cat-transmon architecture matches that of an unbiased-noise architecture with physical error rates in the range 10^{−5}–10^{−4}. |
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| ISSN: | 2691-3399 |