112-Gb/s DSP-Based PAM-4 Transceivers for Large-Scale Ethernet Switching Systems
As modern ASICs integrate several hundred interconnect ports in a large package, ASIC Serdes design faces challenging performance, power, and area targets. Thanks to architectural advancements and technology scaling, a DSP-based transceiver has demonstrated better than 40-dB loss compensation with c...
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| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
| Published: |
IEEE
2024-01-01
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| Series: | IEEE Open Journal of the Solid-State Circuits Society |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/10738450/ |
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