112-Gb/s DSP-Based PAM-4 Transceivers for Large-Scale Ethernet Switching Systems
As modern ASICs integrate several hundred interconnect ports in a large package, ASIC Serdes design faces challenging performance, power, and area targets. Thanks to architectural advancements and technology scaling, a DSP-based transceiver has demonstrated better than 40-dB loss compensation with c...
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IEEE
2024-01-01
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Series: | IEEE Open Journal of the Solid-State Circuits Society |
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Online Access: | https://ieeexplore.ieee.org/document/10738450/ |
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author | Henry Park Mohammed Abdullatif Ehung Chen Tamer Ali |
author_facet | Henry Park Mohammed Abdullatif Ehung Chen Tamer Ali |
author_sort | Henry Park |
collection | DOAJ |
description | As modern ASICs integrate several hundred interconnect ports in a large package, ASIC Serdes design faces challenging performance, power, and area targets. Thanks to architectural advancements and technology scaling, a DSP-based transceiver has demonstrated better than 40-dB loss compensation with competitive power and area that enabled very large-scale Serdes integration in a single package. This article reviews two recent publications for long-reach ASIC Serdes designed in 5- and 7-nm FinFET. With detailed discussions on design challenges from major building blocks, TX/RX/PLL, a novel TX data path bandwidth extension technique by a feedback equalizer is proposed with silicon data. |
format | Article |
id | doaj-art-02d715dd5aee4119a7bacba3f6f12bff |
institution | Kabale University |
issn | 2644-1349 |
language | English |
publishDate | 2024-01-01 |
publisher | IEEE |
record_format | Article |
series | IEEE Open Journal of the Solid-State Circuits Society |
spelling | doaj-art-02d715dd5aee4119a7bacba3f6f12bff2025-01-25T00:03:20ZengIEEEIEEE Open Journal of the Solid-State Circuits Society2644-13492024-01-01427728910.1109/OJSSCS.2024.348865410738450112-Gb/s DSP-Based PAM-4 Transceivers for Large-Scale Ethernet Switching SystemsHenry Park0https://orcid.org/0009-0007-5202-7108Mohammed Abdullatif1Ehung Chen2https://orcid.org/0009-0003-0357-0471Tamer Ali3High-Speed Serdes Design Team, Mediatek USA, Irvine, CA, USAHigh-Speed Serdes Design Team, Mediatek USA, Irvine, CA, USAHigh-Speed Serdes Design Team, Mediatek USA, Irvine, CA, USAHigh-Speed Serdes Design Team, Mediatek USA, Irvine, CA, USAAs modern ASICs integrate several hundred interconnect ports in a large package, ASIC Serdes design faces challenging performance, power, and area targets. Thanks to architectural advancements and technology scaling, a DSP-based transceiver has demonstrated better than 40-dB loss compensation with competitive power and area that enabled very large-scale Serdes integration in a single package. This article reviews two recent publications for long-reach ASIC Serdes designed in 5- and 7-nm FinFET. With detailed discussions on design challenges from major building blocks, TX/RX/PLL, a novel TX data path bandwidth extension technique by a feedback equalizer is proposed with silicon data.https://ieeexplore.ieee.org/document/10738450/112 Gb/sASICDSPEthernet switchlong reachPAM-4 |
spellingShingle | Henry Park Mohammed Abdullatif Ehung Chen Tamer Ali 112-Gb/s DSP-Based PAM-4 Transceivers for Large-Scale Ethernet Switching Systems IEEE Open Journal of the Solid-State Circuits Society 112 Gb/s ASIC DSP Ethernet switch long reach PAM-4 |
title | 112-Gb/s DSP-Based PAM-4 Transceivers for Large-Scale Ethernet Switching Systems |
title_full | 112-Gb/s DSP-Based PAM-4 Transceivers for Large-Scale Ethernet Switching Systems |
title_fullStr | 112-Gb/s DSP-Based PAM-4 Transceivers for Large-Scale Ethernet Switching Systems |
title_full_unstemmed | 112-Gb/s DSP-Based PAM-4 Transceivers for Large-Scale Ethernet Switching Systems |
title_short | 112-Gb/s DSP-Based PAM-4 Transceivers for Large-Scale Ethernet Switching Systems |
title_sort | 112 gb s dsp based pam 4 transceivers for large scale ethernet switching systems |
topic | 112 Gb/s ASIC DSP Ethernet switch long reach PAM-4 |
url | https://ieeexplore.ieee.org/document/10738450/ |
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